5359b938c0
This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4 and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at the same time, to make I/O ASIC DMA interrupts functional. Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted by software by writing 0 to the respective bit in I/O ASIC's System Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1 bits are handled in the CPU (the difference is SIR DMA interrupt bits are R/W0C so there's no need for an RMW cycle). Otherwise the handler is reentered over and over again. The only current user is the DEC LANCE Ethernet driver and its extremely uncommon DMA memory error handler that does not care when exactly the interrupt is cleared. Anticipating the use of DMA interrupts by the Zilog SCC driver this change however exports clear_ioasic_dma_irq for device drivers to choose the right application-specific sequence to clear the request explicitly rather than calling it implicitly in the .irq_eoi handler of `struct irq_chip'. Previously these interrupts were cleared in the .end handler of the said structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5826/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
40 lines
915 B
C
40 lines
915 B
C
/*
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* include/asm-mips/dec/ioasic.h
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*
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* DEC I/O ASIC access operations.
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*
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* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ASM_DEC_IOASIC_H
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#define __ASM_DEC_IOASIC_H
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#include <linux/spinlock.h>
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#include <linux/types.h>
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extern spinlock_t ioasic_ssr_lock;
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extern volatile u32 *ioasic_base;
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static inline void ioasic_write(unsigned int reg, u32 v)
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{
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ioasic_base[reg / 4] = v;
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}
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static inline u32 ioasic_read(unsigned int reg)
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{
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return ioasic_base[reg / 4];
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}
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extern void clear_ioasic_dma_irq(unsigned int irq);
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extern void init_ioasic_irqs(int base);
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extern int dec_ioasic_clocksource_init(void);
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#endif /* __ASM_DEC_IOASIC_H */
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