8c84014f3b
On 64-bit kernels, we don't need it any more: we handle context tracking directly on entry from user mode and exit to user mode. On 32-bit kernels, we don't support context tracking at all, so these callbacks had no effect. Note: this doesn't change do_page_fault(). Before we do that, we need to make sure that there is no code that can page fault from kernel mode with CONTEXT_USER. The 32-bit fast system call stack argument code is the only offender I'm aware of right now. Signed-off-by: Andy Lutomirski <luto@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Denys Vlasenko <vda.linux@googlemail.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Kees Cook <keescook@chromium.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: paulmck@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/ae22f4dfebd799c916574089964592be218151f9.1435952415.git.luto@kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* P5 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/traps.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* By default disabled */
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int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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static void pentium_machine_check(struct pt_regs *regs, long error_code)
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{
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u32 loaddr, hi, lotype;
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ist_enter(regs);
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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printk(KERN_EMERG
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"CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
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smp_processor_id(), loaddr, lotype);
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if (lotype & (1<<5)) {
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printk(KERN_EMERG
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"CPU#%d: Possible thermal failure (CPU on fire ?).\n",
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smp_processor_id());
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}
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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ist_exit(regs);
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}
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/* Set up machine check reporting for processors with Intel style MCE: */
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/* Default P5 to off as its often misconnected: */
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if (!mce_p5_enabled)
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return;
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/* Check for MCE support: */
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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machine_check_vector = pentium_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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/* Read registers before enabling: */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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printk(KERN_INFO
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"Intel old style machine check architecture supported.\n");
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/* Enable MCE: */
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cr4_set_bits(X86_CR4_MCE);
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printk(KERN_INFO
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"Intel old style machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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