On the 34K the redundant cache operations were causing excessive stalls resulting in realtime code running on the second VPE missing its deadline. For all other platforms this patch is just a significant performance improvment as illustrated by below benchmark numbers. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K 25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K 4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K 4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K 34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K 34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385 TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K Original patch by me with enhancements by Atsushi Nemoto. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
179 lines
4.5 KiB
C
179 lines
4.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PAGE_H
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#define _ASM_PAGE_H
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#ifdef __KERNEL__
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#include <spaces.h>
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/*
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* PAGE_SHIFT determines the page size
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*/
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#ifdef CONFIG_PAGE_SIZE_4KB
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#define PAGE_SHIFT 12
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#endif
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#ifdef CONFIG_PAGE_SIZE_8KB
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#define PAGE_SHIFT 13
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#endif
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#ifdef CONFIG_PAGE_SIZE_16KB
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#define PAGE_SHIFT 14
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#endif
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#ifdef CONFIG_PAGE_SIZE_64KB
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#define PAGE_SHIFT 16
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#endif
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
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#ifndef __ASSEMBLY__
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#include <asm/cpu-features.h>
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extern void clear_page(void * page);
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extern void copy_page(void * to, void * from);
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extern unsigned long shm_align_mask;
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static inline unsigned long pages_do_alias(unsigned long addr1,
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unsigned long addr2)
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{
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return (addr1 ^ addr2) & shm_align_mask;
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}
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struct page;
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static inline void clear_user_page(void *addr, unsigned long vaddr,
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struct page *page)
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{
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extern void (*flush_data_cache_page)(unsigned long addr);
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clear_page(addr);
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if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
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flush_data_cache_page((unsigned long)addr);
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}
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static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
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struct page *to)
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{
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extern void (*flush_data_cache_page)(unsigned long addr);
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copy_page(vto, vfrom);
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if (!cpu_has_ic_fills_f_dc ||
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pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
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flush_data_cache_page((unsigned long)vto);
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}
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/*
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* These are used to make use of C type-checking..
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*/
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#ifdef CONFIG_64BIT_PHYS_ADDR
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#ifdef CONFIG_CPU_MIPS32
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typedef struct { unsigned long pte_low, pte_high; } pte_t;
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#define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
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#else
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typedef struct { unsigned long long pte; } pte_t;
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#define pte_val(x) ((x).pte)
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#endif
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#else
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typedef struct { unsigned long pte; } pte_t;
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#define pte_val(x) ((x).pte)
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#endif
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#define __pte(x) ((pte_t) { (x) } )
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/*
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* For 3-level pagetables we defines these ourselves, for 2-level the
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* definitions are supplied by <asm-generic/pgtable-nopmd.h>.
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*/
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#ifdef CONFIG_64BIT
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typedef struct { unsigned long pmd; } pmd_t;
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#define pmd_val(x) ((x).pmd)
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#define __pmd(x) ((pmd_t) { (x) } )
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#endif
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/*
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* Right now we don't support 4-level pagetables, so all pud-related
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* definitions come from <asm-generic/pgtable-nopud.h>.
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*/
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/*
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* Finall the top of the hierarchy, the pgd
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*/
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typedef struct { unsigned long pgd; } pgd_t;
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#define pgd_val(x) ((x).pgd)
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#define __pgd(x) ((pgd_t) { (x) } )
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/*
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* Manipulate page protection bits
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*/
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typedef struct { unsigned long pgprot; } pgprot_t;
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#define pgprot_val(x) ((x).pgprot)
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#define __pgprot(x) ((pgprot_t) { (x) } )
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/*
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* On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
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* pair of pages we only have a single global bit per pair of pages. When
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* writing to the TLB make sure we always have the bit set for both pages
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* or none. This macro is used to access the `buddy' of the pte we're just
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* working on.
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*/
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#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
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#endif /* !__ASSEMBLY__ */
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/* to align the pointer to the (next) page boundary */
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#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
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#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
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#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
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#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
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#ifdef CONFIG_FLATMEM
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#define pfn_valid(pfn) ((pfn) < max_mapnr)
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#elif defined(CONFIG_SPARSEMEM)
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/* pfn_valid is defined in linux/mmzone.h */
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#elif defined(CONFIG_NEED_MULTIPLE_NODES)
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#define pfn_valid(pfn) \
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({ \
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unsigned long __pfn = (pfn); \
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int __n = pfn_to_nid(__pfn); \
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((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
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NODE_DATA(__n)->node_spanned_pages) \
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: 0); \
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})
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#endif
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
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#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
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#ifdef CONFIG_LIMITED_DMA
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#define WANT_PAGE_VIRTUAL
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#endif
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#include <asm-generic/memory_model.h>
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#include <asm-generic/page.h>
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#endif /* defined (__KERNEL__) */
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#endif /* _ASM_PAGE_H */
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