android_kernel_oneplus_msm8998/arch
Andi Kleen e29c75d4fb x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+
[upstream cc51e5428ea54f575d49cfcede1d4cb3a72b4ec4 for 4.4.
Note there might be still a trivial conflict with the backport
for b0a182f875689647b014bc01d36b340217792852, but should
be easy to resolve]

On Nehalem and newer core CPUs the CPU cache internally uses 44 bits
physical address space. The L1TF workaround is limited by this internal
cache address width, and needs to have one bit free there for the
mitigation to work.

Older client systems report only 36bit physical address space so the range
check decides that L1TF is not mitigated for a 36bit phys/32GB system with
some memory holes.

But since these actually have the larger internal cache width this warning
is bogus because it would only really be needed if the system had more than
43bits of memory.

Add a new internal x86_cache_bits field. Normally it is the same as the
physical bits field reported by CPUID, but for Nehalem and newerforce it to
be at least 44bits.

Change the L1TF memory size warning to use the new cache_bits field to
avoid bogus warnings and remove the bogus comment about memory size.

Fixes: 17dbca119312 ("x86/speculation/l1tf: Add sysfs reporting for l1tf")
Reported-by: George Anchev <studio@anchev.net>
Reported-by: Christopher Snowhill <kode54@gmail.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Michael Hocko <mhocko@suse.com>
Cc: vbabka@suse.cz
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20180824170351.34874-1-andi@firstfloor.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-09-19 22:49:00 +02:00
..
alpha sys: don't hold uts_sem while accessing userspace memory 2018-09-09 20:04:35 +02:00
arc ARC: [plat-axs*]: Enable SWAP 2018-09-19 22:48:56 +02:00
arm irqchip/gic-v3: Add missing barrier to 32bit version of gic_read_iar() 2018-09-15 09:40:41 +02:00
arm64 arm64: mm: check for upper PAGE_SHIFT bits in pfn_valid() 2018-09-05 09:18:38 +02:00
avr32
blackfin pinctrl: adi2: Fix Kconfig build problem 2017-12-20 10:05:00 +01:00
c6x
cris
frv futex: Remove duplicated code and fix undefined behaviour 2018-05-26 08:48:50 +02:00
h8300
hexagon futex: Remove duplicated code and fix undefined behaviour 2018-05-26 08:48:50 +02:00
ia64 futex: Remove duplicated code and fix undefined behaviour 2018-05-26 08:48:50 +02:00
m32r
m68k m68k: fix "bad page state" oops on ColdFire boot 2018-08-24 13:26:57 +02:00
metag metag/uaccess: Check access_ok in strncpy_from_user 2017-05-25 14:30:16 +02:00
microblaze microblaze: Fix simpleImage format generation 2018-08-06 16:24:39 +02:00
mips MIPS: WARN_ON invalid DMA cache maintenance, not BUG_ON 2018-09-19 22:48:59 +02:00
mn10300 mn10300/misalignment: Use SIGSEGV SEGV_MAPERR to report a failed user copy 2018-02-16 20:09:47 +01:00
nios2 nios2: reserve boot memory for device tree 2017-04-12 12:38:34 +02:00
openrisc kthread: fix boot hang (regression) on MIPS/OpenRISC 2018-09-19 22:48:55 +02:00
parisc parisc: Remove unnecessary barriers from spinlock.h 2018-08-24 13:27:01 +02:00
powerpc powerpc/pseries: Avoid using the size greater than RTAS_ERROR_LOG_MAX. 2018-09-15 09:40:39 +02:00
s390 s390/lib: use expoline for all bcr instructions 2018-09-15 09:40:42 +02:00
score
sh sh: New gcc support 2018-06-06 16:46:20 +02:00
sparc sys: don't hold uts_sem while accessing userspace memory 2018-09-09 20:04:35 +02:00
tile futex: Remove duplicated code and fix undefined behaviour 2018-05-26 08:48:50 +02:00
um um: Use POSIX ucontext_t instead of struct ucontext 2018-04-24 09:32:08 +02:00
unicore32
x86 x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+ 2018-09-19 22:49:00 +02:00
xtensa signal/xtensa: Consistenly use SIGBUS in do_unaligned_user 2018-07-03 11:21:26 +02:00
.gitignore
Kconfig