40b15b2808
The PIIX4_ICTLR* and PIIX4_OCW* defines are not used by any other files. Remove them. The only file (other than fixup-malta.c which includes piix4.h in patch #1) containing "#include <asm/mips-boards/piix4.h>" is arch/mips/mti-malta/malta-int.c whose first version is actually "1da177e4c3:arch/mips/mips-boards/malta/malta_int.c". In that version, in the function get_int(), things in piix4.h are used. But now malta-int.c no longer needs those stuff. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
46 lines
1.8 KiB
C
46 lines
1.8 KiB
C
/*
|
|
* Carsten Langgaard, carstenl@mips.com
|
|
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
|
* Copyright (C) 2013 Imagination Technologies Ltd.
|
|
*
|
|
* This program is free software; you can distribute it and/or modify it
|
|
* under the terms of the GNU General Public License (Version 2) as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
* for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along
|
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
|
*
|
|
* Register definitions for Intel PIIX4 South Bridge Device.
|
|
*/
|
|
#ifndef __ASM_MIPS_BOARDS_PIIX4_H
|
|
#define __ASM_MIPS_BOARDS_PIIX4_H
|
|
|
|
/* PIRQX Route Control */
|
|
#define PIIX4_FUNC0_PIRQRC 0x60
|
|
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
|
|
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
|
|
#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
|
|
/* Top Of Memory */
|
|
#define PIIX4_FUNC0_TOM 0x69
|
|
#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
|
|
/* Deterministic Latency Control */
|
|
#define PIIX4_FUNC0_DLC 0x82
|
|
#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
|
|
#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
|
|
#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
|
|
|
|
/* IDE Timing */
|
|
#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
|
|
#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
|
|
#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
|
|
#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
|
|
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
|
|
#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
|
|
|
|
#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
|