d0bfd7c9b1
SMEM is a software construct built on top of a DDR reserved region and sometimes a device memory region called RPM message ram. Having the RPM message ram in the smem DT node's reg property leads to the smem node being located in different places depending on if the message ram is being used or not. Let's add a qcom specific property, qcom,rpm-msg-ram, and point to the device memory from the SMEM node via a phandle. As SMEM is a software construct, it really needs to reside at the root of the DT regardless of whether it's using the message ram or not. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
342 lines
7.4 KiB
Text
342 lines
7.4 KiB
Text
/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include "skeleton.dtsi"
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/ {
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model = "Qualcomm MSM8974";
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compatible = "qcom,msm8974";
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interrupt-parent = <&intc>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_region: smem@fa00000 {
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reg = <0xfa00000 0x200000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <1 9 0xf04>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@2 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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cpu-idle-states = <&CPU_SPC>;
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};
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cpu@3 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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cpu-idle-states = <&CPU_SPC>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc",
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"arm,idle-state";
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entry-latency-us = <150>;
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exit-latency-us = <200>;
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min-residency-us = <2000>;
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};
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 7 0xf04>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <19200000>;
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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clock-frequency = <19200000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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saw0: power-controller@f9089000 {
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compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
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};
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saw1: power-controller@f9099000 {
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compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
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};
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saw2: power-controller@f90a9000 {
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compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw3: power-controller@f90b9000 {
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compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
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reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
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};
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saw_l2: power-controller@f9012000 {
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compatible = "qcom,saw2";
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reg = <0xf9012000 0x1000>;
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regulator;
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};
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acc0: clock-controller@f9088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
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};
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acc1: clock-controller@f9098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
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};
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acc2: clock-controller@f90a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
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};
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acc3: clock-controller@f90b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-msm8974";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0xfc400000 0x4000>;
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};
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tcsr_mutex_block: syscon@fd484000 {
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compatible = "syscon";
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reg = <0xfd484000 0x2000>;
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};
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mmcc: clock-controller@fd8c0000 {
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compatible = "qcom,mmcc-msm8974";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0xfd8c0000 0x6000>;
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};
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tcsr_mutex: tcsr-mutex {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x80>;
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#hwlock-cells = <1>;
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};
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rpm_msg_ram: memory@fc428000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0xfc428000 0x4000>;
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};
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blsp1_uart2: serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0 108 0x0>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f98a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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msmgpio: pinctrl@fd510000 {
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compatible = "qcom,msm8974-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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};
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blsp_i2c11: i2c@f9967000 {
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status = "disable";
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compatible = "qcom,i2c-qup-v2.1.1";
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reg = <0xf9967000 0x1000>;
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interrupts = <0 105 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spmi_bus: spmi@fc4cf000 {
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compatible = "qcom,spmi-pmic-arb";
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reg-names = "core", "intr", "cnfg";
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reg = <0xfc4cf000 0x1000>,
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<0xfc4cb000 0x1000>,
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<0xfc4ca000 0x1000>;
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interrupt-names = "periph_irq";
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interrupts = <0 190 0>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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};
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};
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