c4a202c8ae
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2011
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "db8500-regs.h"
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#include "id.h"
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static void __iomem *l2x0_base;
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static int __init ux500_l2x0_unlock(void)
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{
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int i;
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/*
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* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
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* apparently locks both caches before jumping to the kernel. The
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* l2x0 core will not touch the unlock registers if the l2x0 is
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* already enabled, so we do it right here instead. The PL310 has
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* 8 sets of registers, one per possible CPU.
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*/
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for (i = 0; i < 8; i++) {
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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}
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return 0;
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}
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static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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/*
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* We can't write to secure registers as we are in non-secure
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* mode, until we have some SMI service available.
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*/
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}
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static int __init ux500_l2x0_init(void)
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{
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if (cpu_is_u8500_family() || cpu_is_ux540_family())
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l2x0_base = __io_address(U8500_L2CC_BASE);
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else
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/* Non-Ux500 platform */
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return -ENODEV;
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/* Unlock before init */
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ux500_l2x0_unlock();
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outer_cache.write_sec = ux500_l2c310_write_sec;
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if (of_have_populated_dt())
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l2x0_of_init(0x3e000000, 0xc00f0fff);
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else
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l2x0_init(l2x0_base, 0x3e000000, 0xc00f0fff);
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return 0;
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}
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early_initcall(ux500_l2x0_init);
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