cb809b1a5e
The simpler AT91x40 processors do not have the same power management controller as the new AT91 devices. They do have a simpler power controller module that we can use to disable the CPU clock at idle time. Add code to support that. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* arch/arm/mach-at91/include/mach/system.h
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*
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* Copyright (C) 2003 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_SYSTEM_H
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#define __ASM_ARCH_SYSTEM_H
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#include <mach/hardware.h>
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#include <mach/at91_st.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91_pmc.h>
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static inline void arch_idle(void)
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{
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#ifndef CONFIG_DEBUG_KERNEL
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/*
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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#ifdef AT91_PS
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at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
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#else
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at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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#endif
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#else
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/*
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* Set the processor (CP15) into 'Wait for Interrupt' mode.
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* Unlike disabling the processor clock via the PMC (above)
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* this allows the processor to be woken via JTAG.
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*/
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cpu_do_idle();
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#endif
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}
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void (*at91_arch_reset)(void);
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static inline void arch_reset(char mode, const char *cmd)
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{
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/* call the CPU-specific reset function */
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if (at91_arch_reset)
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(at91_arch_reset)();
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}
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#endif
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