Tony Lindgren 03208cc69f clk: ti: Fix FAPLL parent enable bit handling ... Commit 163152cbbe ("clk: ti: Add support for FAPLL on dm816x") added basic support for the FAPLL on dm818x, but has a bug for the parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3) but the code is doing a shift on it. This means the parent PLL won't get disabled even if all it's child synthesizers are disabled. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>		2015-02-25 12:06:29 -08:00
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apll.c
autoidle.c
clk-2xxx.c
clk-3xxx-legacy.c
clk-3xxx.c
clk-7xx.c
clk-33xx.c
clk-43xx.c
clk-44xx.c
clk-54xx.c
clk-816x.c
clk-dra7-atl.c
clk.c
clock.h
clockdomain.c
composite.c
divider.c
dpll.c
fapll.c	clk: ti: Fix FAPLL parent enable bit handling	2015-02-25 12:06:29 -08:00
fixed-factor.c
gate.c
interface.c
Makefile
mux.c