c461731836
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is a CC-NUMA system that every chip (node) has its own local memory and cache coherency is maintained by hardware. The 64-bit physical memory address format is as follows: 0x-0000-YZZZ-ZZZZ-ZZZZ The high 16 bits should be 0, which means the real physical address supported by Loongson-3 is 48-bit. The "Y" bits is the base address of each node, which can be also considered as the node-id. The "Z" bits is the address offset within a node, which means every node has a 44 bits address space. Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally, because many other MIPS CPUs have also extended their address spaces. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
|
|
* Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
|
|
* Insititute of Computing Technology
|
|
* Author: Xiang Gao, gaoxiang@ict.ac.cn
|
|
* Huacai Chen, chenhc@lemote.com
|
|
* Xiaofu Meng, Shuangshuang Zhang
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
#ifndef _ASM_MACH_MMZONE_H
|
|
#define _ASM_MACH_MMZONE_H
|
|
|
|
#include <boot_param.h>
|
|
#define NODE_ADDRSPACE_SHIFT 44
|
|
#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
|
|
#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL
|
|
#define NODE2_ADDRSPACE_OFFSET 0x200000000000UL
|
|
#define NODE3_ADDRSPACE_OFFSET 0x300000000000UL
|
|
|
|
#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
|
|
|
|
#define LEVELS_PER_SLICE 128
|
|
|
|
struct slice_data {
|
|
unsigned long irq_enable_mask[2];
|
|
int level_to_irq[LEVELS_PER_SLICE];
|
|
};
|
|
|
|
struct hub_data {
|
|
cpumask_t h_cpus;
|
|
unsigned long slice_map;
|
|
unsigned long irq_alloc_mask[2];
|
|
struct slice_data slice[2];
|
|
};
|
|
|
|
struct node_data {
|
|
struct pglist_data pglist;
|
|
struct hub_data hub;
|
|
cpumask_t cpumask;
|
|
};
|
|
|
|
extern struct node_data *__node_data[];
|
|
|
|
#define NODE_DATA(n) (&__node_data[(n)]->pglist)
|
|
#define hub_data(n) (&__node_data[(n)]->hub)
|
|
|
|
extern void setup_zero_pages(void);
|
|
extern void __init prom_init_numa_memory(void);
|
|
|
|
#endif /* _ASM_MACH_MMZONE_H */
|