df96ed8dce
ITC (Interrupt Threshold Control) is used to set the maximum rate at which the host/device controller will issue interrupts. The default value is 8 (1ms) for it. EHCI core will modify it to 1, but device mode keeps it as default value. In some use cases like Android ADB, it only has one usb request for each direction, and maximum payload data is only 4KB, so the speed is 4MB/s at most, it needs controller to trigger interrupt as fast as possible to increase the speed. The USB performance will be better if the interrupt can be triggered faster. Reduce ITC value is benefit for USB performance, but the interrupt number is increased at the same time, it may increase cpu utilization too. Most of use case cares about performance, but some may care about cpu utilization, so, we leave a platform interface for user. We set ITC as 1 (1 micro-frame) as default value which is aligned with ehci core default value. Signed-off-by: Peter Chen <peter.chen@freescale.com>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
|
|
* Platform data for the chipidea USB dual role controller
|
|
*/
|
|
|
|
#ifndef __LINUX_USB_CHIPIDEA_H
|
|
#define __LINUX_USB_CHIPIDEA_H
|
|
|
|
#include <linux/usb/otg.h>
|
|
|
|
struct ci_hdrc;
|
|
struct ci_hdrc_platform_data {
|
|
const char *name;
|
|
/* offset of the capability registers */
|
|
uintptr_t capoffset;
|
|
unsigned power_budget;
|
|
struct phy *phy;
|
|
/* old usb_phy interface */
|
|
struct usb_phy *usb_phy;
|
|
enum usb_phy_interface phy_mode;
|
|
unsigned long flags;
|
|
#define CI_HDRC_REGS_SHARED BIT(0)
|
|
#define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2)
|
|
#define CI_HDRC_DISABLE_STREAMING BIT(3)
|
|
/*
|
|
* Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
|
|
* but otg is not supported (no register otgsc).
|
|
*/
|
|
#define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
|
|
#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
|
|
#define CI_HDRC_FORCE_FULLSPEED BIT(6)
|
|
#define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7)
|
|
#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8)
|
|
enum usb_dr_mode dr_mode;
|
|
#define CI_HDRC_CONTROLLER_RESET_EVENT 0
|
|
#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
|
|
void (*notify_event) (struct ci_hdrc *ci, unsigned event);
|
|
struct regulator *reg_vbus;
|
|
bool tpl_support;
|
|
/* interrupt threshold setting */
|
|
u32 itc_setting;
|
|
};
|
|
|
|
/* Default offset of capability registers */
|
|
#define DEF_CAPOFFSET 0x100
|
|
|
|
/* Add ci hdrc device */
|
|
struct platform_device *ci_hdrc_add_device(struct device *dev,
|
|
struct resource *res, int nres,
|
|
struct ci_hdrc_platform_data *platdata);
|
|
/* Remove ci hdrc device */
|
|
void ci_hdrc_remove_device(struct platform_device *pdev);
|
|
|
|
#endif
|