90015c8938
This patch unifies the cpu specific interrupt setup functions for interrupt controller blocks such as ipr, intc2 and intc. There is no point in having separate functions for each interrupt controller, so let's clean this up. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* SH7785 Setup
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*
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* Copyright (C) 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xffea0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 41, 43, 42 },
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}, {
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.mapbase = 0xffeb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 44, 45, 47, 46 },
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},
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/*
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* The rest of these all have multiplexed IRQs
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*/
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{
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.mapbase = 0xffec0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 60, 60, 60, 60 },
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}, {
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.mapbase = 0xffed0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 61, 61, 61, 61 },
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}, {
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.mapbase = 0xffee0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 62, 62, 62, 62 },
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}, {
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.mapbase = 0xffef0000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 63, 63, 63, 63 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7785_devices[] __initdata = {
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&sci_device,
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};
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static int __init sh7785_devices_setup(void)
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{
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return platform_add_devices(sh7785_devices,
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ARRAY_SIZE(sh7785_devices));
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}
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__initcall(sh7785_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{ 28, 0, 24, 0, 0, 2 }, /* TMU0 */
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{ 40, 8, 24, 0, 2, 3 }, /* SCIF0 ERI */
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{ 41, 8, 24, 0, 2, 3 }, /* SCIF0 RXI */
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{ 42, 8, 24, 0, 2, 3 }, /* SCIF0 BRI */
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{ 43, 8, 24, 0, 2, 3 }, /* SCIF0 TXI */
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{ 44, 8, 16, 0, 3, 3 }, /* SCIF1 ERI */
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{ 45, 8, 16, 0, 3, 3 }, /* SCIF1 RXI */
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{ 46, 8, 16, 0, 3, 3 }, /* SCIF1 BRI */
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{ 47, 8, 16, 0, 3, 3 }, /* SCIF1 TXI */
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{ 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */
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{ 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */
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{ 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */
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{ 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */
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{ 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */
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{ 60, 8, 8, 0, 4, 3 }, /* SCIF2 ERI, RXI, BRI, TXI */
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{ 60, 8, 0, 0, 5, 3 }, /* SCIF3 ERI, RXI, BRI, TXI */
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{ 60, 12, 24, 0, 6, 3 }, /* SCIF4 ERI, RXI, BRI, TXI */
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{ 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */
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};
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static struct intc2_desc intc2_irq_desc __read_mostly = {
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.prio_base = 0xffd40000,
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.msk_base = 0xffd40038,
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.mskclr_base = 0xffd4003c,
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.intc2_data = intc2_irq_table,
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.nr_irqs = ARRAY_SIZE(intc2_irq_table),
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.chip = {
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.name = "INTC2-sh7785",
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},
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};
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void __init plat_irq_setup(void)
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{
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register_intc2_controller(&intc2_irq_desc);
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}
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