Douglas Anderson b6e216cc56 clk: rockchip: Don't yell about bad mmc phases when getting ... commit 6943b839721ad4a31ad2bacf6e71b21f2dfe3134 upstream. At boot time, my rk3288-veyron devices yell with 8 lines that look like this: [ 0.000000] rockchip_mmc_get_phase: invalid clk rate This is because the clock framework at clk_register() time tries to get the phase but we don't have a parent yet. While the errors appear to be harmless they are still ugly and, in general, we don't want yells like this in the log unless they are important. There's no real reason to be yelling here. We can still return -EINVAL to indicate that the phase makes no sense without a parent. If someone really tries to do tuning and the clock is reported as 0 then we'll see the yells in rockchip_mmc_set_phase(). Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2019-09-21 07:12:44 +02:00
..
clk-cpu.c
clk-inverter.c
clk-mmc-phase.c	clk: rockchip: Don't yell about bad mmc phases when getting	2019-09-21 07:12:44 +02:00
clk-pll.c	clk: rockchip: don't use clk_ APIs in the pll init-callback	2015-10-01 14:58:28 -07:00
clk-rk3188.c	clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks	2016-04-12 09:09:02 -07:00
clk-rk3288.c	clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288	2019-06-22 08:18:20 +02:00
clk-rk3368.c	clk: rockchip: rk3368: fix hdmi_cec gate-register	2016-04-12 09:09:02 -07:00
clk-rockchip.c
clk.c	clk: rockchip: free memory in error cases when registering clock branches	2016-05-11 11:21:12 +02:00
clk.h
Makefile
softrst.c