-----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAltYMlwACgkQONu9yGCS aT5ZmxAAjAWUndXt7fTUyHgxkoG61sEkdX4jcsp6NFwQMudU0UHx4/kcZE+HdMjL VU8BZtdUg+jMLXM4erVBpQRKY9YHIPi8nWMTm1UjduMCxVD6dVL1HU6/RXl1cYIx rf/opYOimqT9lYCeffmd9ai2zEEJKSt7/avddcJY4qHiqLan27gbUdAq2H26aM/5 LUzAaSBzhq3VYo9Q5zv03b1+tORAxh2BIffZjGEFe8SQQl1o63WqwV4RxEhV/Bjt hBgl/6B/+EHtQnYnbnoOT/an9Ma15ik4/z3vVv6yRLNK+hS5T31OKcYCsUrjp6O+ TQVaVLWWmn/VpIHAMkrhBs9Xxg5GmRziF77AkzyC506tK268M2+IoY77ursVl1YK STaOwUcLUlKLbl5OADqMpYtNU9ybkP+MmgDZsIEXz9UiCZM721fL5Au2PHuzaYOD 2nE2EQb04It4k9GN8FStv2KPIiKUCEXi9MlNsHGPs6Mc+fliIigoKPhpU5JG+sxR eJgPMNv4OWhwXWTd1wf0Gy5X+i0lQlwlGgIHFfSB8vzArJ0Y/yuPj2a6xhQshOza Ivq7JudHvxYxhDSWYoCKgtTgzMdSBbJ3xjOoUUHy4ryamYeyaMvgFjsaCTMr0dsw 76BkgNTbpsip+I77a9h4Ozlk5QE7h61EsqjmZBkGVqLYjrUQ/IU= =X4tZ -----END PGP SIGNATURE----- Merge 4.4.144 into android-4.4 Changes in 4.4.144 KVM/Eventfd: Avoid crash when assign and deassign specific eventfd in parallel. x86/MCE: Remove min interval polling limitation fat: fix memory allocation failure handling of match_strdup() ALSA: rawmidi: Change resized buffers atomically ARC: Fix CONFIG_SWAP ARC: mm: allow mprotect to make stack mappings executable mm: memcg: fix use after free in mem_cgroup_iter() ipv4: Return EINVAL when ping_group_range sysctl doesn't map to user ns ipv6: fix useless rol32 call on hash lib/rhashtable: consider param->min_size when setting initial table size net/ipv4: Set oif in fib_compute_spec_dst net: phy: fix flag masking in __set_phy_supported ptp: fix missing break in switch tg3: Add higher cpu clock for 5762. net: Don't copy pfmemalloc flag in __copy_skb_header() skbuff: Unconditionally copy pfmemalloc in __skb_clone() xhci: Fix perceived dead host due to runtime suspend race with event handler x86/paravirt: Make native_save_fl() extern inline x86/cpufeatures: Add CPUID_7_EDX CPUID leaf x86/cpufeatures: Add Intel feature bits for Speculation Control x86/cpufeatures: Add AMD feature bits for Speculation Control x86/msr: Add definitions for new speculation control MSRs x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown x86/cpufeature: Blacklist SPEC_CTRL/PRED_CMD on early Spectre v2 microcodes x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support x86/cpufeatures: Clean up Spectre v2 related CPUID flags x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel x86/pti: Mark constant arrays as __initconst x86/asm/entry/32: Simplify pushes of zeroed pt_regs->REGs x86/entry/64/compat: Clear registers for compat syscalls, to reduce speculation attack surface x86/speculation: Update Speculation Control microcode blacklist x86/speculation: Correct Speculation Control microcode blacklist again x86/speculation: Clean up various Spectre related details x86/speculation: Fix up array_index_nospec_mask() asm constraint x86/speculation: Add <asm/msr-index.h> dependency x86/xen: Zero MSR_IA32_SPEC_CTRL before suspend x86/mm: Factor out LDT init from context init x86/mm: Give each mm TLB flush generation a unique ID x86/speculation: Use Indirect Branch Prediction Barrier in context switch x86/spectre_v2: Don't check microcode versions when running under hypervisors x86/speculation: Use IBRS if available before calling into firmware x86/speculation: Move firmware_restrict_branch_speculation_*() from C to CPP x86/speculation: Remove Skylake C2 from Speculation Control microcode blacklist selftest/seccomp: Fix the flag name SECCOMP_FILTER_FLAG_TSYNC selftest/seccomp: Fix the seccomp(2) signature xen: set cpu capabilities from xen_start_kernel() x86/amd: don't set X86_BUG_SYSRET_SS_ATTRS when running under Xen x86/nospec: Simplify alternative_msr_write() x86/bugs: Concentrate bug detection into a separate function x86/bugs: Concentrate bug reporting into a separate function x86/bugs: Read SPEC_CTRL MSR during boot and re-use reserved bits x86/bugs, KVM: Support the combination of guest and host IBRS x86/cpu: Rename Merrifield2 to Moorefield x86/cpu/intel: Add Knights Mill to Intel family x86/bugs: Expose /sys/../spec_store_bypass x86/cpufeatures: Add X86_FEATURE_RDS x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigation x86/bugs/intel: Set proper CPU features and setup RDS x86/bugs: Whitelist allowed SPEC_CTRL MSR values x86/bugs/AMD: Add support to disable RDS on Fam[15, 16, 17]h if requested x86/speculation: Create spec-ctrl.h to avoid include hell prctl: Add speculation control prctls x86/process: Optimize TIF checks in __switch_to_xtra() x86/process: Correct and optimize TIF_BLOCKSTEP switch x86/process: Optimize TIF_NOTSC switch x86/process: Allow runtime control of Speculative Store Bypass x86/speculation: Add prctl for Speculative Store Bypass mitigation nospec: Allow getting/setting on non-current task proc: Provide details on speculation flaw mitigations seccomp: Enable speculation flaw mitigations prctl: Add force disable speculation seccomp: Use PR_SPEC_FORCE_DISABLE seccomp: Add filter flag to opt-out of SSB mitigation seccomp: Move speculation migitation control to arch code x86/speculation: Make "seccomp" the default mode for Speculative Store Bypass x86/bugs: Rename _RDS to _SSBD proc: Use underscores for SSBD in 'status' Documentation/spec_ctrl: Do some minor cleanups x86/bugs: Fix __ssb_select_mitigation() return type x86/bugs: Make cpu_show_common() static x86/bugs: Fix the parameters alignment and missing void x86/cpu: Make alternative_msr_write work for 32-bit code x86/speculation: Use synthetic bits for IBRS/IBPB/STIBP x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRS x86/cpufeatures: Disentangle SSBD enumeration x86/cpu/AMD: Fix erratum 1076 (CPB bit) x86/cpufeatures: Add FEATURE_ZEN x86/speculation: Handle HT correctly on AMD x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRL x86/speculation: Add virtualized speculative store bypass disable support x86/speculation: Rework speculative_store_bypass_update() x86/bugs: Unify x86_spec_ctrl_{set_guest, restore_host} x86/bugs: Expose x86_spec_ctrl_base directly x86/bugs: Remove x86_spec_ctrl_set() x86/bugs: Rework spec_ctrl base and mask logic x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG x86/bugs: Rename SSBD_NO to SSB_NO x86/xen: Add call of speculative_store_bypass_ht_init() to PV paths x86/cpu: Re-apply forced caps every time CPU caps are re-read block: do not use interruptible wait anywhere clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 ubi: Introduce vol_ignored() ubi: Rework Fastmap attach base code ubi: Be more paranoid while seaching for the most recent Fastmap ubi: Fix races around ubi_refill_pools() ubi: Fix Fastmap's update_vol() ubi: fastmap: Erase outdated anchor PEBs during attach Linux 4.4.144 Change-Id: Ia3e9b2b7bc653cba68b76878d34f8fcbbc007a13 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
318 lines
10 KiB
C
318 lines
10 KiB
C
/* thread_info.h: low-level thread information
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*
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* Copyright (C) 2002 David Howells (dhowells@redhat.com)
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* - Incorporating suggestions made by Linus Torvalds and Dave Miller
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*/
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#ifndef _ASM_X86_THREAD_INFO_H
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#define _ASM_X86_THREAD_INFO_H
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#include <linux/compiler.h>
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#include <asm/page.h>
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#include <asm/percpu.h>
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#include <asm/types.h>
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/*
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* TOP_OF_KERNEL_STACK_PADDING is a number of unused bytes that we
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* reserve at the top of the kernel stack. We do it because of a nasty
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* 32-bit corner case. On x86_32, the hardware stack frame is
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* variable-length. Except for vm86 mode, struct pt_regs assumes a
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* maximum-length frame. If we enter from CPL 0, the top 8 bytes of
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* pt_regs don't actually exist. Ordinarily this doesn't matter, but it
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* does in at least one case:
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*
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* If we take an NMI early enough in SYSENTER, then we can end up with
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* pt_regs that extends above sp0. On the way out, in the espfix code,
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* we can read the saved SS value, but that value will be above sp0.
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* Without this offset, that can result in a page fault. (We are
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* careful that, in this case, the value we read doesn't matter.)
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*
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* In vm86 mode, the hardware frame is much longer still, so add 16
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* bytes to make room for the real-mode segments.
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*
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* x86_64 has a fixed-length stack frame.
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*/
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#ifdef CONFIG_X86_32
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# ifdef CONFIG_VM86
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# define TOP_OF_KERNEL_STACK_PADDING 16
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# else
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# define TOP_OF_KERNEL_STACK_PADDING 8
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# endif
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#else
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# define TOP_OF_KERNEL_STACK_PADDING 0
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#endif
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/*
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* low level task data that entry.S needs immediate access to
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* - this struct should fit entirely inside of one cache line
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* - this struct shares the supervisor stack pages
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*/
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#ifndef __ASSEMBLY__
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struct task_struct;
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#include <asm/cpufeature.h>
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#include <linux/atomic.h>
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struct thread_info {
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struct task_struct *task; /* main task structure */
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__u32 flags; /* low level flags */
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__u32 status; /* thread synchronous flags */
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__u32 cpu; /* current CPU */
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mm_segment_t addr_limit;
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unsigned int sig_on_uaccess_error:1;
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unsigned int uaccess_err:1; /* uaccess failed */
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};
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.flags = 0, \
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.cpu = 0, \
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.addr_limit = KERNEL_DS, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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#define init_stack (init_thread_union.stack)
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#else /* !__ASSEMBLY__ */
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#include <asm/asm-offsets.h>
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#endif
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/*
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* thread information flags
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* - these are process state flags that various assembly files
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* may need to access
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* - pending work-to-be-done flags are in LSW
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* - other flags in MSW
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* Warning: layout of LSW is hardcoded in entry.S
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*/
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#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
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#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
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#define TIF_SIGPENDING 2 /* signal pending */
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#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
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#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/
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#define TIF_SSBD 5 /* Reduced data speculation */
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#define TIF_SYSCALL_EMU 6 /* syscall emulation active */
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#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
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#define TIF_SECCOMP 8 /* secure computing */
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#define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */
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#define TIF_UPROBE 12 /* breakpointed or singlestepping */
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#define TIF_NOTSC 16 /* TSC is not accessible in userland */
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#define TIF_IA32 17 /* IA32 compatibility process */
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#define TIF_FORK 18 /* ret_from_fork */
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#define TIF_NOHZ 19 /* in adaptive nohz mode */
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#define TIF_MEMDIE 20 /* is terminating due to OOM killer */
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#define TIF_POLLING_NRFLAG 21 /* idle is polling for TIF_NEED_RESCHED */
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#define TIF_IO_BITMAP 22 /* uses I/O bitmap */
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#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */
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#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */
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#define TIF_LAZY_MMU_UPDATES 27 /* task is updating the mmu lazily */
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#define TIF_SYSCALL_TRACEPOINT 28 /* syscall tracepoint instrumentation */
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#define TIF_ADDR32 29 /* 32-bit address space on 64 bits */
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#define TIF_X32 30 /* 32-bit native x86-64 binary */
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#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
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#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
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#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
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#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
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#define _TIF_SSBD (1 << TIF_SSBD)
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#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
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#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
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#define _TIF_SECCOMP (1 << TIF_SECCOMP)
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#define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
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#define _TIF_UPROBE (1 << TIF_UPROBE)
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#define _TIF_NOTSC (1 << TIF_NOTSC)
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#define _TIF_IA32 (1 << TIF_IA32)
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#define _TIF_FORK (1 << TIF_FORK)
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#define _TIF_NOHZ (1 << TIF_NOHZ)
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#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
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#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP)
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#define _TIF_FORCED_TF (1 << TIF_FORCED_TF)
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#define _TIF_BLOCKSTEP (1 << TIF_BLOCKSTEP)
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#define _TIF_LAZY_MMU_UPDATES (1 << TIF_LAZY_MMU_UPDATES)
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#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
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#define _TIF_ADDR32 (1 << TIF_ADDR32)
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#define _TIF_X32 (1 << TIF_X32)
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/* work to do in syscall_trace_enter() */
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#define _TIF_WORK_SYSCALL_ENTRY \
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(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_EMU | _TIF_SYSCALL_AUDIT | \
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_TIF_SECCOMP | _TIF_SINGLESTEP | _TIF_SYSCALL_TRACEPOINT | \
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_TIF_NOHZ)
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/* work to do on any return to user space */
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#define _TIF_ALLWORK_MASK \
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((0x0000FFFF & ~_TIF_SECCOMP) | _TIF_SYSCALL_TRACEPOINT | \
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_TIF_NOHZ)
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/* flags to check in __switch_to() */
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#define _TIF_WORK_CTXSW \
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(_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD)
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#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
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#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
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#define STACK_WARN (THREAD_SIZE/8)
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/*
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* macros/functions for gaining access to the thread information structure
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*
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* preempt_count needs to be 1 initially, until the scheduler is functional.
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*/
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#ifndef __ASSEMBLY__
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static inline struct thread_info *current_thread_info(void)
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{
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return (struct thread_info *)(current_top_of_stack() - THREAD_SIZE);
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}
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/*
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* Walks up the stack frames to make sure that the specified object is
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* entirely contained by a single stack frame.
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*
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* Returns:
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* 1 if within a frame
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* -1 if placed across a frame boundary (or outside stack)
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* 0 unable to determine (no frame pointers, etc)
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*/
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static inline int arch_within_stack_frames(const void * const stack,
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const void * const stackend,
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const void *obj, unsigned long len)
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{
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#if defined(CONFIG_FRAME_POINTER)
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const void *frame = NULL;
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const void *oldframe;
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oldframe = __builtin_frame_address(1);
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if (oldframe)
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frame = __builtin_frame_address(2);
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/*
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* low ----------------------------------------------> high
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* [saved bp][saved ip][args][local vars][saved bp][saved ip]
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* ^----------------^
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* allow copies only within here
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*/
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while (stack <= frame && frame < stackend) {
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/*
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* If obj + len extends past the last frame, this
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* check won't pass and the next frame will be 0,
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* causing us to bail out and correctly report
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* the copy as invalid.
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*/
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if (obj + len <= frame)
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return obj >= oldframe + 2 * sizeof(void *) ? 1 : -1;
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oldframe = frame;
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frame = *(const void * const *)frame;
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}
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return -1;
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#else
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return 0;
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#endif
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}
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#else /* !__ASSEMBLY__ */
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#ifdef CONFIG_X86_64
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# define cpu_current_top_of_stack (cpu_tss + TSS_sp0)
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#endif
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/* Load thread_info address into "reg" */
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#define GET_THREAD_INFO(reg) \
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_ASM_MOV PER_CPU_VAR(cpu_current_top_of_stack),reg ; \
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_ASM_SUB $(THREAD_SIZE),reg ;
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/*
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* ASM operand which evaluates to a 'thread_info' address of
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* the current task, if it is known that "reg" is exactly "off"
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* bytes below the top of the stack currently.
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*
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* ( The kernel stack's size is known at build time, it is usually
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* 2 or 4 pages, and the bottom of the kernel stack contains
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* the thread_info structure. So to access the thread_info very
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* quickly from assembly code we can calculate down from the
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* top of the kernel stack to the bottom, using constant,
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* build-time calculations only. )
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*
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* For example, to fetch the current thread_info->flags value into %eax
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* on x86-64 defconfig kernels, in syscall entry code where RSP is
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* currently at exactly SIZEOF_PTREGS bytes away from the top of the
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* stack:
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*
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* mov ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS), %eax
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*
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* will translate to:
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*
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* 8b 84 24 b8 c0 ff ff mov -0x3f48(%rsp), %eax
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*
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* which is below the current RSP by almost 16K.
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*/
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#define ASM_THREAD_INFO(field, reg, off) ((field)+(off)-THREAD_SIZE)(reg)
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#endif
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/*
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* Thread-synchronous status.
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*
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* This is different from the flags in that nobody else
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* ever touches our thread-synchronous status, so we don't
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* have to worry about atomic accesses.
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*/
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#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
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#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */
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#ifndef __ASSEMBLY__
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#define HAVE_SET_RESTORE_SIGMASK 1
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static inline void set_restore_sigmask(void)
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{
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struct thread_info *ti = current_thread_info();
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ti->status |= TS_RESTORE_SIGMASK;
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WARN_ON(!test_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags));
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}
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static inline void clear_restore_sigmask(void)
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{
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current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
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}
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static inline bool test_restore_sigmask(void)
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{
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return current_thread_info()->status & TS_RESTORE_SIGMASK;
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}
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static inline bool test_and_clear_restore_sigmask(void)
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{
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struct thread_info *ti = current_thread_info();
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if (!(ti->status & TS_RESTORE_SIGMASK))
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return false;
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ti->status &= ~TS_RESTORE_SIGMASK;
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return true;
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}
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static inline bool is_ia32_task(void)
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{
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#ifdef CONFIG_X86_32
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return true;
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#endif
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#ifdef CONFIG_IA32_EMULATION
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if (current_thread_info()->status & TS_COMPAT)
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return true;
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#endif
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return false;
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}
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/*
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* Force syscall return via IRET by making it look as if there was
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* some work pending. IRET is our most capable (but slowest) syscall
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* return path, which is able to restore modified SS, CS and certain
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* EFLAGS values that other (fast) syscall return instructions
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* are not able to restore properly.
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*/
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#define force_iret() set_thread_flag(TIF_NOTIFY_RESUME)
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#endif /* !__ASSEMBLY__ */
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#ifndef __ASSEMBLY__
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extern void arch_task_cache_init(void);
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extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
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extern void arch_release_task_struct(struct task_struct *tsk);
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#endif
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#endif /* _ASM_X86_THREAD_INFO_H */
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