2008-10-22 22:26:29 -07:00
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#ifndef _ASM_X86_PGTABLE_2LEVEL_H
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#define _ASM_X86_PGTABLE_2LEVEL_H
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2005-04-16 15:20:36 -07:00
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#define pte_ERROR(e) \
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2012-05-21 19:50:07 -07:00
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pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
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2005-04-16 15:20:36 -07:00
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#define pgd_ERROR(e) \
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2012-05-21 19:50:07 -07:00
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pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
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2005-04-16 15:20:36 -07:00
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/*
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* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pte(pte_t *ptep , pte_t pte)
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{
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*ptep = pte;
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}
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2008-01-30 13:32:58 +01:00
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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}
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2006-12-07 02:14:08 +01:00
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2008-01-30 13:32:58 +01:00
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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2005-04-16 15:20:36 -07:00
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2008-01-30 13:32:58 +01:00
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static inline void native_pmd_clear(pmd_t *pmdp)
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{
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native_set_pmd(pmdp, __pmd(0));
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}
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[PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Proposed fix for ptep_get_and_clear_full PAE bug. Pte_clear had the same bug,
so use the same fix for both. Turns out pmd_clear had it as well, but pgds
are not affected.
The problem is rather intricate. Page table entries in PAE mode are 64-bits
wide, but the only atomic 8-byte write operation available in 32-bit mode is
cmpxchg8b, which is expensive (at least on P4), and thus avoided. But it can
happen that the processor may prefetch entries into the TLB in the middle of an
operation which clears a page table entry. So one must always clear the P-bit
in the low word of the page table entry first when clearing it.
Since the sequence *ptep = __pte(0) leaves the order of the write dependent on
the compiler, it must be coded explicitly as a clear of the low word followed
by a clear of the high word. Further, there must be a write memory barrier
here to enforce proper ordering by the compiler (and, in the future, by the
processor as well).
On > 4GB memory machines, the implementation of pte_clear for PAE was clearly
deficient, as it could leave virtual mappings of physical memory above 4GB
aliased to memory below 4GB in the TLB. The implementation of
ptep_get_and_clear_full has a similar bug, although not nearly as likely to
occur, since the mappings being cleared are in the process of being destroyed,
and should never be dereferenced again.
But, as luck would have it, it is possible to trigger bugs even without ever
dereferencing these bogus TLB mappings, even if the clear is followed fairly
soon after with a TLB flush or invalidation. The problem is that memory above
4GB may now be aliased into the first 4GB of memory, and in fact, may hit a
region of memory with non-memory semantics. These regions include AGP and PCI
space. As such, these memory regions are not cached by the processor. This
introduces the bug.
The processor can speculate memory operations, including memory writes, as long
as they are committed with the proper ordering. Speculating a memory write to
a linear address that has a bogus TLB mapping is possible. Normally, the
speculation is harmless. But for cached memory, it does leave the falsely
speculated cacheline unmodified, but in a dirty state. This cache line will be
eventually written back. If this cacheline happens to intersect a region of
memory that is not protected by the cache coherency protocol, it can corrupt
data in I/O memory, which is generally a very bad thing to do, and can cause
total system failure or just plain undefined behavior.
These bugs are extremely unlikely, but the severity is of such magnitude, and
the fix so simple that I think fixing them immediately is justified. Also,
they are nearly impossible to debug.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-27 11:32:29 -07:00
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2008-03-23 01:03:08 -07:00
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static inline void native_pte_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *xp)
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2007-05-02 19:27:19 +02:00
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{
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2008-01-30 13:32:58 +01:00
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*xp = native_make_pte(0);
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2007-05-02 19:27:19 +02:00
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}
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2007-05-02 19:27:19 +02:00
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#ifdef CONFIG_SMP
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2007-05-02 19:27:13 +02:00
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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return __pte(xchg(&xp->pte_low, 0));
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}
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2007-05-02 19:27:19 +02:00
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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2006-09-25 23:32:30 -07:00
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2011-01-13 15:47:01 -08:00
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#ifdef CONFIG_SMP
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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{
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return __pmd(xchg((pmdval_t *)xp, 0));
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}
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#else
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#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
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#endif
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2013-11-15 14:14:00 -08:00
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/* Bit manipulation helper on pte/pgoff entry */
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static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift,
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unsigned long mask, unsigned int leftshift)
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{
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return ((value >> rightshift) & mask) << leftshift;
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}
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2005-04-16 15:20:36 -07:00
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/* Encode and de-code a swap entry */
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2015-02-10 14:11:22 -08:00
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#define SWP_TYPE_BITS 5
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2008-12-16 11:35:24 +00:00
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#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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#define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \
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& ((1U << SWP_TYPE_BITS) - 1))
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#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { \
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((type) << (_PAGE_BIT_PRESENT + 1)) \
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| ((offset) << SWP_OFFSET_SHIFT) })
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2005-04-16 15:20:36 -07:00
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
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2008-01-30 13:32:57 +01:00
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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2005-04-16 15:20:36 -07:00
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2018-06-13 15:48:24 -07:00
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/* No inverted PFNs on 2 level page tables */
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static inline u64 protnone_mask(u64 val)
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{
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return 0;
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}
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static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
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{
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return val;
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}
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static inline bool __pte_needs_invert(u64 val)
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{
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return false;
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}
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2008-10-22 22:26:29 -07:00
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#endif /* _ASM_X86_PGTABLE_2LEVEL_H */
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