irqchip: GICv3: Check if GIC register access is controlled
Add support to configure ITS registers only if higher exception levels have not already configured them. Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d Signed-off-by: Hanumant Singh <hanumant@codeaurora.org> Signed-off-by: Puja Gupta <pujag@codeaurora.org> [abhimany: resolved minor merge conflict] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
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2 changed files with 11 additions and 2 deletions
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@ -27,6 +27,13 @@ config ARM_GIC_V3_ITS
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bool
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select PCI_MSI_IRQ_DOMAIN
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config ARM_GIC_V3_ACL
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bool "GICv3 Access control"
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depends on ARM_GIC_V3
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help
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Access to GIC ITS address space is controlled by EL2.
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Kernel has no permission to access ITS
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config ARM_GIC_V3_NO_ACCESS_CONTROL
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bool "GICv3 No Access Control Configuration"
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depends on ARM_GIC_V3
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@ -594,7 +594,8 @@ static void gic_cpu_init(void)
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gic_cpu_config(rbase, gic_redist_wait_for_rwp);
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/* Give LPIs a spin */
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if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
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if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
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!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
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its_cpu_init();
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/* initialise system registers */
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@ -1035,7 +1036,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
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set_handle_irq(gic_handle_irq);
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if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
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if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
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!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
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its_init(node, &gic_data.rdists, gic_data.domain);
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gic_chip.flags |= gic_arch_extn.flags;
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