evie/android_kernel_oneplus_msm8998
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irqchip: GICv3: Check if GIC register access is controlled

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Add support to configure ITS registers only if higher
exception levels have not already configured them.

Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d
Signed-off-by: Hanumant Singh <hanumant@codeaurora.org>
Signed-off-by: Puja Gupta <pujag@codeaurora.org>
[abhimany: resolved minor merge conflict]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
This commit is contained in:
Abhimanyu Kapur 2016-02-12 17:34:46 -08:00 • committed by David Keitel
parent c36ce4acc9
commit 0574be1ea8
2 changed files with 11 additions and 2 deletions
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7
drivers/irqchip/Kconfig
View file

@ -27,6 +27,13 @@ config ARM_GIC_V3_ITS
bool
select PCI_MSI_IRQ_DOMAIN
config ARM_GIC_V3_ACL
bool "GICv3 Access control"
depends on ARM_GIC_V3
help
Access to GIC ITS address space is controlled by EL2.
Kernel has no permission to access ITS
config ARM_GIC_V3_NO_ACCESS_CONTROL
bool "GICv3 No Access Control Configuration"
depends on ARM_GIC_V3

6
drivers/irqchip/irq-gic-v3.c
View file

@ -594,7 +594,8 @@ static void gic_cpu_init(void)
gic_cpu_config(rbase, gic_redist_wait_for_rwp);
/* Give LPIs a spin */
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
its_cpu_init();
/* initialise system registers */
@ -1035,7 +1036,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
set_handle_irq(gic_handle_irq);
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
its_init(node, &gic_data.rdists, gic_data.domain);
gic_chip.flags |= gic_arch_extn.flags;