mhi: core: Flush CPU write buffer before DMA op

CPU write buffer must be flushed before a DMA operation
is signaled to the device.

CRs-Fixed: 812602
Change-Id: I304671fd1a403d6d897b47641910bc112310b674
Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
This commit is contained in:
Andrei Danaila 2015-03-27 16:56:31 -07:00 committed by David Keitel
parent c966ff457f
commit 0af9a4590b

View file

@ -609,6 +609,10 @@ enum MHI_STATUS mhi_queue_xfer(struct mhi_client_handle *client_handle,
MHI_TRB_SET_INFO(TX_TRB_TYPE, pkt_loc, MHI_PKT_TYPE_TRANSFER);
MHI_TX_TRB_SET_LEN(TX_TRB_LEN, pkt_loc, buf_len);
/* Ensure writes to descriptor are flushed */
wmb();
mhi_log(MHI_MSG_VERBOSE,
"Channel %d Has buf size of %d and buf addr %lx, flags 0x%x\n",
chan, buf_len, (uintptr_t)buf, mhi_flags);