mhi: core: Flush CPU write buffer before DMA op
CPU write buffer must be flushed before a DMA operation is signaled to the device. CRs-Fixed: 812602 Change-Id: I304671fd1a403d6d897b47641910bc112310b674 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
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@ -609,6 +609,10 @@ enum MHI_STATUS mhi_queue_xfer(struct mhi_client_handle *client_handle,
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MHI_TRB_SET_INFO(TX_TRB_TYPE, pkt_loc, MHI_PKT_TYPE_TRANSFER);
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MHI_TX_TRB_SET_LEN(TX_TRB_LEN, pkt_loc, buf_len);
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/* Ensure writes to descriptor are flushed */
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wmb();
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mhi_log(MHI_MSG_VERBOSE,
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"Channel %d Has buf size of %d and buf addr %lx, flags 0x%x\n",
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chan, buf_len, (uintptr_t)buf, mhi_flags);
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