staging: comedi: ni_mio_common: open code the M-Series regmap offsets
Remove the enum m_series_register_offsets values that are only used in the lookup tables for the STC to M-Series register mapping and just open code the values. Having the extra level of indirection does not add any additional clarity and it gets rid of some of the CamelCase symbols. Some of the registers are not currently used by the driver so the mappings were not present in the original switch code. Add the missing register mappings to the lookup tables. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
05dd0c9fcb
commit
2475c548e7
2 changed files with 79 additions and 146 deletions
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@ -314,14 +314,14 @@ struct mio_regmap {
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};
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};
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static const struct mio_regmap m_series_stc_write_regmap[] = {
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static const struct mio_regmap m_series_stc_write_regmap[] = {
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[Interrupt_A_Ack_Register] = { M_Offset_Interrupt_A_Ack, 2 },
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[Interrupt_A_Ack_Register] = { 0x104, 2 },
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[Interrupt_B_Ack_Register] = { M_Offset_Interrupt_B_Ack, 2 },
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[Interrupt_B_Ack_Register] = { 0x106, 2 },
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[AI_Command_2_Register] = { M_Offset_AI_Command_2, 2 },
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[AI_Command_2_Register] = { 0x108, 2 },
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[AO_Command_2_Register] = { M_Offset_AO_Command_2, 2 },
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[AO_Command_2_Register] = { 0x10a, 2 },
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[G_Command_Register(0)] = { M_Offset_G0_Command, 2 },
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[G_Command_Register(0)] = { 0x10c, 2 },
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[G_Command_Register(1)] = { M_Offset_G1_Command, 2 },
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[G_Command_Register(1)] = { 0x10e, 2 },
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[AI_Command_1_Register] = { M_Offset_AI_Command_1, 2 },
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[AI_Command_1_Register] = { 0x110, 2 },
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[AO_Command_1_Register] = { M_Offset_AO_Command_1, 2 },
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[AO_Command_1_Register] = { 0x112, 2 },
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[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[DIO_Output_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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/*
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/*
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* DIO_Output_Register maps to:
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* DIO_Output_Register maps to:
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@ -329,51 +329,59 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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* { M_Offset_SCXI_Serial_Data_Out, 1 }
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* { M_Offset_SCXI_Serial_Data_Out, 1 }
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*/
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*/
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[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[DIO_Control_Register] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
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[AI_Mode_1_Register] = { M_Offset_AI_Mode_1, 2 },
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[AI_Mode_1_Register] = { 0x118, 2 },
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[AI_Mode_2_Register] = { M_Offset_AI_Mode_2, 2 },
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[AI_Mode_2_Register] = { 0x11a, 2 },
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[AI_SI_Load_A_Registers] = { M_Offset_AI_SI_Load_A, 4 },
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[AI_SI_Load_A_Registers] = { 0x11c, 4 },
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[AI_SC_Load_A_Registers] = { M_Offset_AI_SC_Load_A, 4 },
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[AI_SI_Load_B_Registers] = { 0x120, 4 },
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[AI_SI2_Load_A_Register] = { M_Offset_AI_SI2_Load_A, 4 },
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[AI_SC_Load_A_Registers] = { 0x124, 4 },
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[AI_SI2_Load_B_Register] = { M_Offset_AI_SI2_Load_B, 4 },
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[AI_SC_Load_B_Registers] = { 0x128, 4 },
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[G_Mode_Register(0)] = { M_Offset_G0_Mode, 2 },
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[AI_SI2_Load_A_Register] = { 0x12c, 4 },
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[G_Mode_Register(1)] = { M_Offset_G1_Mode, 2 },
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[AI_SI2_Load_B_Register] = { 0x130, 4 },
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[G_Load_A_Register(0)] = { M_Offset_G0_Load_A, 4 },
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[G_Mode_Register(0)] = { 0x134, 2 },
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[G_Load_B_Register(0)] = { M_Offset_G0_Load_B, 4 },
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[G_Mode_Register(1)] = { 0x136, 2 },
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[G_Load_A_Register(1)] = { M_Offset_G1_Load_A, 4 },
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[G_Load_A_Register(0)] = { 0x138, 4 },
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[G_Load_B_Register(1)] = { M_Offset_G1_Load_B, 4 },
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[G_Load_B_Register(0)] = { 0x13c, 4 },
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[G_Input_Select_Register(0)] = { M_Offset_G0_Input_Select, 2 },
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[G_Load_A_Register(1)] = { 0x140, 4 },
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[G_Input_Select_Register(1)] = { M_Offset_G1_Input_Select, 2 },
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[G_Load_B_Register(1)] = { 0x144, 4 },
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[AO_Mode_1_Register] = { M_Offset_AO_Mode_1, 2 },
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[G_Input_Select_Register(0)] = { 0x148, 2 },
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[AO_Mode_2_Register] = { M_Offset_AO_Mode_2, 2 },
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[G_Input_Select_Register(1)] = { 0x14a, 2 },
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[AO_UI_Load_A_Register] = { M_Offset_AO_UI_Load_A, 4 },
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[AO_Mode_1_Register] = { 0x14c, 2 },
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[AO_BC_Load_A_Register] = { M_Offset_AO_BC_Load_A, 4 },
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[AO_Mode_2_Register] = { 0x14e, 2 },
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[AO_UC_Load_A_Register] = { M_Offset_AO_UC_Load_A, 4 },
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[AO_UI_Load_A_Register] = { 0x150, 4 },
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[Clock_and_FOUT_Register] = { M_Offset_Clock_and_FOUT, 2 },
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[AO_UI_Load_B_Register] = { 0x154, 4 },
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[IO_Bidirection_Pin_Register] = { M_Offset_IO_Bidirection_Pin, 2 },
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[AO_BC_Load_A_Register] = { 0x158, 4 },
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[RTSI_Trig_Direction_Register] = { M_Offset_RTSI_Trig_Direction, 2 },
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[AO_BC_Load_B_Register] = { 0x15c, 4 },
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[Interrupt_Control_Register] = { M_Offset_Interrupt_Control, 2 },
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[AO_UC_Load_A_Register] = { 0x160, 4 },
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[AI_Output_Control_Register] = { M_Offset_AI_Output_Control, 2 },
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[AO_UC_Load_B_Register] = { 0x164, 4 },
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[Analog_Trigger_Etc_Register] = { M_Offset_Analog_Trigger_Etc, 2 },
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[Clock_and_FOUT_Register] = { 0x170, 2 },
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[AI_START_STOP_Select_Register] = { M_Offset_AI_START_STOP_Select, 2 },
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[IO_Bidirection_Pin_Register] = { 0x172, 2 },
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[AI_Trigger_Select_Register] = { M_Offset_AI_Trigger_Select, 2 },
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[RTSI_Trig_Direction_Register] = { 0x174, 2 },
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[AO_Start_Select_Register] = { M_Offset_AO_Start_Select, 2 },
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[Interrupt_Control_Register] = { 0x176, 2 },
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[AO_Trigger_Select_Register] = { M_Offset_AO_Trigger_Select, 2 },
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[AI_Output_Control_Register] = { 0x178, 2 },
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[G_Autoincrement_Register(0)] = { M_Offset_G0_Autoincrement, 2 },
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[Analog_Trigger_Etc_Register] = { 0x17a, 2 },
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[G_Autoincrement_Register(1)] = { M_Offset_G1_Autoincrement, 2 },
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[AI_START_STOP_Select_Register] = { 0x17c, 2 },
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[AO_Mode_3_Register] = { M_Offset_AO_Mode_3, 2 },
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[AI_Trigger_Select_Register] = { 0x17e, 2 },
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[Joint_Reset_Register] = { M_Offset_Joint_Reset, 2 },
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[AI_DIV_Load_A_Register] = { 0x180, 4 },
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[Interrupt_A_Enable_Register] = { M_Offset_Interrupt_A_Enable, 2 },
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[AO_Start_Select_Register] = { 0x184, 2 },
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[Interrupt_B_Enable_Register] = { M_Offset_Interrupt_B_Enable, 2 },
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[AO_Trigger_Select_Register] = { 0x186, 2 },
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[AI_Personal_Register] = { M_Offset_AI_Personal, 2 },
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[G_Autoincrement_Register(0)] = { 0x188, 2 },
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[AO_Personal_Register] = { M_Offset_AO_Personal, 2 },
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[G_Autoincrement_Register(1)] = { 0x18a, 2 },
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[RTSI_Trig_A_Output_Register] = { M_Offset_RTSI_Trig_A_Output, 2 },
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[AO_Mode_3_Register] = { 0x18c, 2 },
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[RTSI_Trig_B_Output_Register] = { M_Offset_RTSI_Trig_B_Output, 2 },
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[Joint_Reset_Register] = { 0x190, 2 },
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[Configuration_Memory_Clear] = { M_Offset_Configuration_Memory_Clear,
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[Interrupt_A_Enable_Register] = { 0x192, 2 },
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2 },
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[Second_IRQ_A_Enable_Register] = { 0, 0 }, /* E-Series only */
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[ADC_FIFO_Clear] = { M_Offset_AI_FIFO_Clear, 2 },
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[Interrupt_B_Enable_Register] = { 0x196, 2 },
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[DAC_FIFO_Clear] = { M_Offset_AO_FIFO_Clear, 2 },
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[Second_IRQ_B_Enable_Register] = { 0, 0 }, /* E-Series only */
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[AO_Output_Control_Register] = { M_Offset_AO_Output_Control, 2 },
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[AI_Personal_Register] = { 0x19a, 2 },
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[AI_Mode_3_Register] = { M_Offset_AI_Mode_3, 2 },
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[AO_Personal_Register] = { 0x19c, 2 },
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[RTSI_Trig_A_Output_Register] = { 0x19e, 2 },
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[RTSI_Trig_B_Output_Register] = { 0x1a0, 2 },
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[RTSI_Board_Register] = { 0, 0 }, /* Unknown */
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[Configuration_Memory_Clear] = { 0x1a4, 2 },
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[ADC_FIFO_Clear] = { 0x1a6, 2 },
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[DAC_FIFO_Clear] = { 0x1a8, 2 },
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[AO_Output_Control_Register] = { 0x1ac, 2 },
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[AI_Mode_3_Register] = { 0x1ae, 2 },
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};
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};
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static void m_series_stc_write(struct comedi_device *dev,
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static void m_series_stc_write(struct comedi_device *dev,
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@ -404,17 +412,24 @@ static void m_series_stc_write(struct comedi_device *dev,
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}
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}
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static const struct mio_regmap m_series_stc_read_regmap[] = {
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static const struct mio_regmap m_series_stc_read_regmap[] = {
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[AI_Status_1_Register] = { M_Offset_AI_Status_1, 2 },
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[AI_Status_1_Register] = { 0x104, 2 },
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[AO_Status_1_Register] = { M_Offset_AO_Status_1, 2 },
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[AO_Status_1_Register] = { 0x106, 2 },
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[G_Status_Register] = { M_Offset_G01_Status, 2 },
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[G_Status_Register] = { 0x108, 2 },
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[AO_Status_2_Register] = { M_Offset_AO_Status_2, 2 },
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[AI_Status_2_Register] = { 0, 0 }, /* Unknown */
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[G_HW_Save_Register(0)] = { M_Offset_G0_HW_Save, 4 },
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[AO_Status_2_Register] = { 0x10c, 2 },
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[G_HW_Save_Register(1)] = { M_Offset_G1_HW_Save, 4 },
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[DIO_Parallel_Input_Register] = { 0, 0 }, /* Unknown */
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[G_Save_Register(0)] = { M_Offset_G0_Save, 4 },
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[G_HW_Save_Register(0)] = { 0x110, 4 },
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[G_Save_Register(1)] = { M_Offset_G1_Save, 4 },
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[G_HW_Save_Register(1)] = { 0x114, 4 },
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[Joint_Status_1_Register] = { M_Offset_Joint_Status_1, 2 },
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[G_Save_Register(0)] = { 0x118, 4 },
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[DIO_Serial_Input_Register] = { M_Offset_SCXI_Serial_Data_In, 1 },
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[G_Save_Register(1)] = { 0x11c, 4 },
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[Joint_Status_2_Register] = { M_Offset_Joint_Status_2, 2 },
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[AO_UI_Save_Registers] = { 0x120, 4 },
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[AO_BC_Save_Registers] = { 0x124, 4 },
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[AO_UC_Save_Registers] = { 0x128, 4 },
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[Joint_Status_1_Register] = { 0x136, 2 },
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[DIO_Serial_Input_Register] = { 0x009, 1 },
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[Joint_Status_2_Register] = { 0x13a, 2 },
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[AI_SI_Save_Registers] = { 0x180, 4 },
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[AI_SC_Save_Registers] = { 0x184, 4 },
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};
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};
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static unsigned int m_series_stc_read(struct comedi_device *dev,
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static unsigned int m_series_stc_read(struct comedi_device *dev,
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@ -924,7 +924,6 @@ enum m_series_register_offsets {
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M_Offset_CDIO_DMA_Select = 0x7, /* write */
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M_Offset_CDIO_DMA_Select = 0x7, /* write */
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M_Offset_SCXI_Status = 0x7, /* read */
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M_Offset_SCXI_Status = 0x7, /* read */
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M_Offset_AI_AO_Select = 0x9, /* write, same offset as e-series */
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M_Offset_AI_AO_Select = 0x9, /* write, same offset as e-series */
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M_Offset_SCXI_Serial_Data_In = 0x9, /* read */
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M_Offset_G0_G1_Select = 0xb, /* write, same offset as e-series */
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M_Offset_G0_G1_Select = 0xb, /* write, same offset as e-series */
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M_Offset_Misc_Command = 0xf,
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M_Offset_Misc_Command = 0xf,
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M_Offset_SCXI_Serial_Data_Out = 0x11,
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M_Offset_SCXI_Serial_Data_Out = 0x11,
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@ -947,88 +946,7 @@ enum m_series_register_offsets {
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M_Offset_PFI_Filter = 0xb0,
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M_Offset_PFI_Filter = 0xb0,
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M_Offset_RTSI_Filter = 0xb4,
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M_Offset_RTSI_Filter = 0xb4,
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M_Offset_SCXI_Legacy_Compatibility = 0xbc,
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M_Offset_SCXI_Legacy_Compatibility = 0xbc,
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M_Offset_Interrupt_A_Ack = 0x104, /* write */
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M_Offset_AI_Status_1 = 0x104, /* read */
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M_Offset_Interrupt_B_Ack = 0x106, /* write */
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M_Offset_AO_Status_1 = 0x106, /* read */
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M_Offset_AI_Command_2 = 0x108, /* write */
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M_Offset_G01_Status = 0x108, /* read */
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M_Offset_AO_Command_2 = 0x10a,
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M_Offset_AO_Status_2 = 0x10c, /* read */
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M_Offset_G0_Command = 0x10c, /* write */
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M_Offset_G1_Command = 0x10e, /* write */
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M_Offset_G0_HW_Save = 0x110,
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M_Offset_G0_HW_Save_High = 0x110,
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M_Offset_AI_Command_1 = 0x110,
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M_Offset_G0_HW_Save_Low = 0x112,
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M_Offset_AO_Command_1 = 0x112,
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M_Offset_G1_HW_Save = 0x114,
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M_Offset_G1_HW_Save_High = 0x114,
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M_Offset_G1_HW_Save_Low = 0x116,
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M_Offset_AI_Mode_1 = 0x118,
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M_Offset_G0_Save = 0x118,
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M_Offset_G0_Save_High = 0x118,
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M_Offset_AI_Mode_2 = 0x11a,
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M_Offset_G0_Save_Low = 0x11a,
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M_Offset_AI_SI_Load_A = 0x11c,
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M_Offset_G1_Save = 0x11c,
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M_Offset_G1_Save_High = 0x11c,
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M_Offset_G1_Save_Low = 0x11e,
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M_Offset_AI_SI_Load_B = 0x120, /* write */
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M_Offset_AO_UI_Save = 0x120, /* read */
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M_Offset_AI_SC_Load_A = 0x124, /* write */
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M_Offset_AO_BC_Save = 0x124, /* read */
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M_Offset_AI_SC_Load_B = 0x128, /* write */
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M_Offset_AO_UC_Save = 0x128, /* read */
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M_Offset_AI_SI2_Load_A = 0x12c,
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M_Offset_AI_SI2_Load_B = 0x130,
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M_Offset_G0_Mode = 0x134,
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M_Offset_G1_Mode = 0x136, /* write */
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M_Offset_Joint_Status_1 = 0x136, /* read */
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M_Offset_G0_Load_A = 0x138,
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M_Offset_Joint_Status_2 = 0x13a,
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M_Offset_G0_Load_B = 0x13c,
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M_Offset_G1_Load_A = 0x140,
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M_Offset_G1_Load_B = 0x144,
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M_Offset_G0_Input_Select = 0x148,
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M_Offset_G1_Input_Select = 0x14a,
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M_Offset_AO_Mode_1 = 0x14c,
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M_Offset_AO_Mode_2 = 0x14e,
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M_Offset_AO_UI_Load_A = 0x150,
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M_Offset_AO_UI_Load_B = 0x154,
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M_Offset_AO_BC_Load_A = 0x158,
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M_Offset_AO_BC_Load_B = 0x15c,
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M_Offset_AO_UC_Load_A = 0x160,
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M_Offset_AO_UC_Load_B = 0x164,
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M_Offset_Clock_and_FOUT = 0x170,
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M_Offset_IO_Bidirection_Pin = 0x172,
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M_Offset_RTSI_Trig_Direction = 0x174,
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M_Offset_Interrupt_Control = 0x176,
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M_Offset_AI_Output_Control = 0x178,
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M_Offset_Analog_Trigger_Etc = 0x17a,
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M_Offset_AI_START_STOP_Select = 0x17c,
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M_Offset_AI_Trigger_Select = 0x17e,
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M_Offset_AI_SI_Save = 0x180, /* read */
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M_Offset_AI_DIV_Load_A = 0x180, /* write */
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M_Offset_AI_SC_Save = 0x184, /* read */
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M_Offset_AO_Start_Select = 0x184, /* write */
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M_Offset_AO_Trigger_Select = 0x186,
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M_Offset_AO_Mode_3 = 0x18c,
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M_Offset_G0_Autoincrement = 0x188,
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M_Offset_G1_Autoincrement = 0x18a,
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M_Offset_Joint_Reset = 0x190,
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M_Offset_Interrupt_A_Enable = 0x192,
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M_Offset_Interrupt_B_Enable = 0x196,
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M_Offset_AI_Personal = 0x19a,
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M_Offset_AO_Personal = 0x19c,
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M_Offset_RTSI_Trig_A_Output = 0x19e,
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M_Offset_RTSI_Trig_B_Output = 0x1a0,
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M_Offset_RTSI_Shared_MUX = 0x1a2,
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M_Offset_RTSI_Shared_MUX = 0x1a2,
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M_Offset_AO_Output_Control = 0x1ac,
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M_Offset_AI_Mode_3 = 0x1ae,
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M_Offset_Configuration_Memory_Clear = 0x1a4,
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M_Offset_AI_FIFO_Clear = 0x1a6,
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M_Offset_AO_FIFO_Clear = 0x1a8,
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M_Offset_G0_Counting_Mode = 0x1b0,
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M_Offset_G0_Counting_Mode = 0x1b0,
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M_Offset_G1_Counting_Mode = 0x1b2,
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M_Offset_G1_Counting_Mode = 0x1b2,
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M_Offset_G0_Second_Gate = 0x1b4,
|
M_Offset_G0_Second_Gate = 0x1b4,
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue