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Merge "ARM: dts: msm: Set the rate for camss vfe clock on SDM660 & SDM630"

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Linux Build Service Account 2017-03-24 12:12:43 -07:00 • committed by Gerrit - the friendly Code Review server
commit 2b2a813f23
2 changed files with 44 additions and 40 deletions
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42
arch/arm/boot/dts/qcom/sdm630-camera.dtsi
View file

@ -451,11 +451,11 @@
<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"camss_ahb_clk",
@ -468,10 +468,12 @@
"csi2_pix_clk", "csi3_pix_clk",
"camss_csi0_clk", "camss_csi1_clk",
"camss_csi2_clk", "camss_csi3_clk",
"vfe0_clk_src",
"camss_vfe_vfe0_clk",
"vfe0_clk_src", "camss_csi_vfe0_clk",
"camss_csi_vfe0_clk",
"vfe1_clk_src",
"camss_vfe_vfe1_clk",
"vfe1_clk_src", "camss_csi_vfe1_clk";
"camss_csi_vfe1_clk";
qcom,clock-rates = <0 0 0 0 0
0 0 0 0
0 0 0 0
@ -490,10 +492,10 @@
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE",
"INIT_RATE", "NO_SET_RATE",
"NO_SET_RATE",
"INIT_RATE", "NO_SET_RATE";
"INIT_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"INIT_RATE",
"NO_SET_RATE", "NO_SET_RATE";
status = "ok";
};
@ -516,23 +518,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
"camss_ahb_clk", "camss_top_ahb_clk",
"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
"camss_vfe_vbif_axi_clk", "vfe_clk_src",
"camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
0 0 0 0 0 0 0 0 0 0 0 480000000 0
0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
0 0 0 0 0 0 480000000 0 0 0 0 0 0
0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
@ -597,23 +599,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
"camss_ahb_clk", "camss_top_ahb_clk",
"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
"camss_vfe_vbif_axi_clk", "vfe_clk_src",
"camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
0 0 0 0 0 0 0 0 0 0 0 480000000 0
0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
0 0 0 0 0 0 480000000 0 0 0 0 0 0
0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418

42
arch/arm/boot/dts/qcom/sdm660-camera.dtsi
View file

@ -454,11 +454,11 @@
<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"camss_ahb_clk",
@ -471,10 +471,12 @@
"csi2_pix_clk", "csi3_pix_clk",
"camss_csi0_clk", "camss_csi1_clk",
"camss_csi2_clk", "camss_csi3_clk",
"vfe0_clk_src",
"camss_vfe_vfe0_clk",
"vfe0_clk_src", "camss_csi_vfe0_clk",
"camss_csi_vfe0_clk",
"vfe1_clk_src",
"camss_vfe_vfe1_clk",
"vfe1_clk_src", "camss_csi_vfe1_clk";
"camss_csi_vfe1_clk";
qcom,clock-rates = <0 0 0 0 0
0 0 0 0
0 0 0 0
@ -493,10 +495,10 @@
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"NO_SET_RATE",
"INIT_RATE", "NO_SET_RATE",
"NO_SET_RATE",
"INIT_RATE", "NO_SET_RATE";
"INIT_RATE",
"NO_SET_RATE", "NO_SET_RATE",
"INIT_RATE",
"NO_SET_RATE", "NO_SET_RATE";
status = "ok";
};
@ -518,23 +520,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
<&clock_mmss VFE0_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
"camss_ahb_clk", "camss_top_ahb_clk",
"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
"camss_vfe_vbif_axi_clk", "vfe_clk_src",
"camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
0 0 0 0 0 0 0 0 0 0 0 480000000 0
0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
0 0 0 0 0 0 480000000 0 0 0 0 0 0
0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
@ -599,23 +601,23 @@
<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
<&clock_mmss MMSS_CAMSS_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
<&clock_mmss VFE1_CLK_SRC>,
<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
"camss_ahb_clk", "camss_top_ahb_clk",
"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
"camss_vfe_clk", "camss_vfe_stream_clk",
"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
"camss_vfe_vbif_axi_clk", "vfe_clk_src",
"camss_vfe_vbif_axi_clk",
"camss_csi_vfe_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
0 0 0 0 0 0 0 0 0 0 0 480000000 0
0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
0 0 0 0 0 0 480000000 0 0 0 0 0 0
0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
status = "ok";
qos-entries = <8>;
qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418