evie/android_kernel_oneplus_msm8998
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mmc: sdhci-msm: Fix issue with power save bit enablement

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The power save bit is currently enabled based on the clock
rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this
clk_rate is updated with the latest value down in this function
sdhci_msm_set_clock(). So during runtime/system resume when the
card is still in initialization phase, the power save bit is
getting enabled when sdhci_msm_set_clock() is called for the
first time based on the previous rate which is wrong.

Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
This commit is contained in:
Sahitya Tummala 2013-08-29 16:21:08 +05:30 • committed by Subhash Jadavani
parent 3118da1c32
commit 2ba264341c
1 changed files with 1 additions and 1 deletions
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2
drivers/mmc/host/sdhci-msm.c
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@ -2405,7 +2405,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
CORE_CLK_PWRSAVE);
if ((msm_host->clk_rate > 400000) &&
if ((clock > 400000) &&
!curr_pwrsave && mmc_host_may_gate_card(host->mmc->card))
writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
| CORE_CLK_PWRSAVE,