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clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCC

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GPLL0 input to the multimedia and graphics clock controllers can
be managed by use of voting registers. Enable this usage and turn
off the inputs when no clocks within these clock controllers need
a GPLL0/GPLL0 divider input.

CRs-Fixed: 1009689
Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2016-06-08 15:05:12 -07:00 • committed by Gerrit - the friendly Code Review server
parent 9d822a9489
commit 389757e59c
4 changed files with 56 additions and 2 deletions
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4
arch/arm/boot/dts/qcom/msmcobalt.dtsi
View file

@ -736,7 +736,7 @@
"dp_link_src", "dp_vco_div",
"extpclk_src";
clocks = <&clock_gcc clk_cxo_clk_src>,
<&clock_gcc clk_gpll0_out_main>,
<&clock_gcc clk_gcc_mmss_gpll0_clk>,
<&clock_gcc clk_gcc_mmss_gpll0_div_clk>,
<&mdss_dsi0_pll clk_dsi0pll_pclk_mux>,
<&mdss_dsi1_pll clk_dsi1pll_pclk_mux>,
@ -755,7 +755,7 @@
vdd_dig-supply = <&pmcobalt_s1_level>;
clock-names = "xo_ao", "gpll0";
clocks = <&clock_gcc clk_cxo_clk_src_ao>,
<&clock_gcc clk_gpll0_out_main>;
<&clock_gcc clk_gcc_gpu_gpll0_clk>;
#clock-cells = <1>;
};

49
drivers/clk/msm/clock-gcc-cobalt.c
View file

@ -164,6 +164,20 @@ static struct pll_vote_clk gpll0_ao = {
DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);
static struct local_vote_clk gcc_mmss_gpll0_clk = {
.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.en_mask = BIT(1),
.base = &virt_base,
.halt_check = DELAY,
.c = {
.dbg_name = "gcc_mmss_gpll0_clk",
.parent = &gpll0.c,
.ops = &clk_ops_vote,
CLK_INIT(gcc_mmss_gpll0_clk.c),
},
};
static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
@ -178,6 +192,34 @@ static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
},
};
static struct local_vote_clk gcc_gpu_gpll0_clk = {
.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.en_mask = BIT(4),
.base = &virt_base,
.halt_check = DELAY,
.c = {
.dbg_name = "gcc_gpu_gpll0_clk",
.parent = &gpll0.c,
.ops = &clk_ops_vote,
CLK_INIT(gcc_gpu_gpll0_clk.c),
},
};
static struct local_vote_clk gcc_gpu_gpll0_div_clk = {
.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
.en_mask = BIT(3),
.base = &virt_base,
.halt_check = DELAY,
.c = {
.dbg_name = "gcc_gpu_gpll0_div_clk",
.parent = &gpll0.c,
.ops = &clk_ops_vote,
CLK_INIT(gcc_gpu_gpll0_div_clk.c),
},
};
static struct pll_vote_clk gpll4 = {
.en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE,
.en_mask = BIT(4),
@ -2535,7 +2577,10 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
CLK_LIST(gpll0),
CLK_LIST(gpll0_ao),
CLK_LIST(gpll0_out_main),
CLK_LIST(gcc_mmss_gpll0_clk),
CLK_LIST(gcc_mmss_gpll0_div_clk),
CLK_LIST(gcc_gpu_gpll0_clk),
CLK_LIST(gcc_gpu_gpll0_div_clk),
CLK_LIST(gpll4),
CLK_LIST(gpll4_out_main),
CLK_LIST(hmss_ahb_clk_src),
@ -2784,6 +2829,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
if (ret)
return ret;
/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
writel_relaxed(0x10003, virt_base + GCC_MMSS_MISC);
writel_relaxed(0x10003, virt_base + GCC_GPU_MISC);
/* Hold an active set vote for the cnoc_periph resource */
clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);

3
include/dt-bindings/clock/msm-clocks-cobalt.h
View file

@ -99,7 +99,10 @@
#define clk_gpll0 0x1ebe3bc4
#define clk_gpll0_out_main 0xe9374de7
#define clk_gpll0_ao 0xa1368304
#define clk_gcc_mmss_gpll0_clk 0x8050f008
#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d
#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4
#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a
#define clk_gpll4 0xb3b5d85b
#define clk_gpll4_out_main 0xa9a0ab9d
#define clk_hmss_ahb_clk_src 0xaec8450f

2
include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
View file

@ -232,6 +232,8 @@
#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014
#define GCC_QSPI_AHB_CBCR 0x90004
#define GCC_QSPI_REF_CBCR 0x90008
#define GCC_MMSS_MISC 0x0902C
#define GCC_GPU_MISC 0x71028
#define GPUCC_GPU_PLL0_PLL_MODE 0x00000
#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C