ARM: dts: msm: limit the maximum PCLK supported for DP on SDM660
Update the dtsi property to limit the maximum pixel clock frequency supported on Display Port for SDM660 to 300 MHz. Change-Id: Iaacb08a310debd0d470d2f16c794fe70b09af2f5 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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@ -494,7 +494,7 @@
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qcom,aux-cfg-settings = [00 13 00 00 0a 28 0a 03 b7 03];
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qcom,logical2physical-lane-map = [00 01 02 03];
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qcom,phy-register-offset = <0x4>;
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qcom,max-pclk-frequency-khz = <593470>;
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qcom,max-pclk-frequency-khz = <300000>;
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qcom,core-supply-entries {
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#address-cells = <1>;
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