Merge "clk: qcom: Remove few graphics clock for sdm660"
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commit
42c03251c6
2 changed files with 0 additions and 34 deletions
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@ -1763,19 +1763,6 @@ static struct clk_branch gcc_gpu_bimc_gfx_clk = {
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},
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};
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static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
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.halt_reg = 0x7100c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x7100c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_bimc_gfx_src_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_gpu_cfg_ahb_clk = {
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.halt_reg = 0x71004,
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.halt_check = BRANCH_VOTED,
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@ -1835,19 +1822,6 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = {
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},
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};
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static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
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.halt_reg = 0x71018,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x71018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_gpu_snoc_dvm_gfx_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_hmss_ahb_clk = {
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.halt_reg = 0x48000,
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.halt_check = BRANCH_HALT_VOTED,
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@ -2675,11 +2649,9 @@ static struct clk_regmap *gcc_660_clocks[] = {
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[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
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[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
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[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
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[GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
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[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
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[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
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[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
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[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
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[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
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[GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
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[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
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@ -2919,9 +2891,7 @@ static const char *const debug_mux_parent_names[] = {
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"gcc_gp2_clk",
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"gcc_gp3_clk",
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"gcc_gpu_bimc_gfx_clk",
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"gcc_gpu_bimc_gfx_src_clk",
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"gcc_gpu_cfg_ahb_clk",
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"gcc_gpu_snoc_dvm_gfx_clk",
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"gcc_hmss_ahb_clk",
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"gcc_hmss_dvm_bus_clk",
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"gcc_hmss_rbcpr_clk",
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@ -3100,9 +3070,7 @@ static struct clk_debug_mux gcc_debug_mux = {
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{ "gcc_gp2_clk", 0x0E0 },
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{ "gcc_gp3_clk", 0x0E1 },
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{ "gcc_gpu_bimc_gfx_clk", 0x13F },
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{ "gcc_gpu_bimc_gfx_src_clk", 0x13E },
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{ "gcc_gpu_cfg_ahb_clk", 0x13B },
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{ "gcc_gpu_snoc_dvm_gfx_clk", 0x141 },
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{ "gcc_hmss_ahb_clk", 0x0BA },
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{ "gcc_hmss_dvm_bus_clk", 0x0BF },
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{ "gcc_hmss_rbcpr_clk", 0x0BC },
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@ -77,11 +77,9 @@
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#define GCC_GP2_CLK 62
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#define GCC_GP3_CLK 63
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#define GCC_GPU_BIMC_GFX_CLK 64
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#define GCC_GPU_BIMC_GFX_SRC_CLK 65
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#define GCC_GPU_CFG_AHB_CLK 66
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#define GCC_GPU_GPLL0_CLK 67
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#define GCC_GPU_GPLL0_DIV_CLK 68
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#define GCC_GPU_SNOC_DVM_GFX_CLK 69
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#define GCC_HMSS_AHB_CLK 70
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#define GCC_HMSS_DVM_BUS_CLK 71
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#define GCC_HMSS_RBCPR_CLK 72
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