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Merge "clk: qcom: Remove few graphics clock for sdm660"

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Linux Build Service Account 2017-01-18 14:23:15 -08:00 • committed by Gerrit - the friendly Code Review server
commit 42c03251c6
2 changed files with 0 additions and 34 deletions
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32
drivers/clk/qcom/gcc-sdm660.c
View file

@ -1763,19 +1763,6 @@ static struct clk_branch gcc_gpu_bimc_gfx_clk = {
}, },
}; };
static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_bimc_gfx_src_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = { static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004, .halt_reg = 0x71004,
.halt_check = BRANCH_VOTED, .halt_check = BRANCH_VOTED,
@ -1835,19 +1822,6 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = {
}, },
}; };
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_ahb_clk = { static struct clk_branch gcc_hmss_ahb_clk = {
.halt_reg = 0x48000, .halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_VOTED,
@ -2675,11 +2649,9 @@ static struct clk_regmap *gcc_660_clocks[] = {
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
[GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
[GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
@ -2919,9 +2891,7 @@ static const char *const debug_mux_parent_names[] = {
"gcc_gp2_clk", "gcc_gp2_clk",
"gcc_gp3_clk", "gcc_gp3_clk",
"gcc_gpu_bimc_gfx_clk", "gcc_gpu_bimc_gfx_clk",
"gcc_gpu_bimc_gfx_src_clk",
"gcc_gpu_cfg_ahb_clk", "gcc_gpu_cfg_ahb_clk",
"gcc_gpu_snoc_dvm_gfx_clk",
"gcc_hmss_ahb_clk", "gcc_hmss_ahb_clk",
"gcc_hmss_dvm_bus_clk", "gcc_hmss_dvm_bus_clk",
"gcc_hmss_rbcpr_clk", "gcc_hmss_rbcpr_clk",
@ -3100,9 +3070,7 @@ static struct clk_debug_mux gcc_debug_mux = {
{ "gcc_gp2_clk", 0x0E0 }, { "gcc_gp2_clk", 0x0E0 },
{ "gcc_gp3_clk", 0x0E1 }, { "gcc_gp3_clk", 0x0E1 },
{ "gcc_gpu_bimc_gfx_clk", 0x13F }, { "gcc_gpu_bimc_gfx_clk", 0x13F },
{ "gcc_gpu_bimc_gfx_src_clk", 0x13E },
{ "gcc_gpu_cfg_ahb_clk", 0x13B }, { "gcc_gpu_cfg_ahb_clk", 0x13B },
{ "gcc_gpu_snoc_dvm_gfx_clk", 0x141 },
{ "gcc_hmss_ahb_clk", 0x0BA }, { "gcc_hmss_ahb_clk", 0x0BA },
{ "gcc_hmss_dvm_bus_clk", 0x0BF }, { "gcc_hmss_dvm_bus_clk", 0x0BF },
{ "gcc_hmss_rbcpr_clk", 0x0BC }, { "gcc_hmss_rbcpr_clk", 0x0BC },

2
include/dt-bindings/clock/qcom,gcc-sdm660.h
View file

@ -77,11 +77,9 @@
#define GCC_GP2_CLK 62 #define GCC_GP2_CLK 62
#define GCC_GP3_CLK 63 #define GCC_GP3_CLK 63
#define GCC_GPU_BIMC_GFX_CLK 64 #define GCC_GPU_BIMC_GFX_CLK 64
#define GCC_GPU_BIMC_GFX_SRC_CLK 65
#define GCC_GPU_CFG_AHB_CLK 66 #define GCC_GPU_CFG_AHB_CLK 66
#define GCC_GPU_GPLL0_CLK 67 #define GCC_GPU_GPLL0_CLK 67
#define GCC_GPU_GPLL0_DIV_CLK 68 #define GCC_GPU_GPLL0_DIV_CLK 68
#define GCC_GPU_SNOC_DVM_GFX_CLK 69
#define GCC_HMSS_AHB_CLK 70 #define GCC_HMSS_AHB_CLK 70
#define GCC_HMSS_DVM_BUS_CLK 71 #define GCC_HMSS_DVM_BUS_CLK 71
#define GCC_HMSS_RBCPR_CLK 72 #define GCC_HMSS_RBCPR_CLK 72