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Merge "ASoC: wcd934x: Update master clock sequence for wcd934x codec"

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Linux Build Service Account 2017-02-09 13:16:10 -08:00 • committed by Gerrit - the friendly Code Review server
commit 43ee8491ea
2 changed files with 9 additions and 6 deletions
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2
sound/soc/codecs/wcd934x/wcd934x.c
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@ -8150,9 +8150,9 @@ static int tavil_dig_core_remove_power_collapse(struct snd_soc_codec *codec)
snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x00); snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x00);
snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x02); snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x02);
snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
wcd9xxx_set_power_state(tavil->wcd9xxx, wcd9xxx_set_power_state(tavil->wcd9xxx,
WCD_REGION_POWER_COLLAPSE_REMOVE, WCD_REGION_POWER_COLLAPSE_REMOVE,

13
sound/soc/codecs/wcd9xxx-resmgr-v2.c
View file

@ -247,15 +247,15 @@ static int wcd_resmgr_enable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr)
* to CLK_SYS_MCLK_PRG * to CLK_SYS_MCLK_PRG
*/ */
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_MCLK_PRG, 0x91, 0x91); WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x80);
wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_MCLK_PRG, 0x30, 0x10);
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00); WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00);
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04, WCD934X_CLK_SYS_MCLK_PRG, 0x01, 0x01);
0x04);
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04, WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00);
0x00);
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD93XX_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, WCD93XX_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
0x01, 0x01); 0x01, 0x01);
@ -308,6 +308,9 @@ static int wcd_resmgr_disable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr)
0x08, 0x08); 0x08, 0x08);
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x02); WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x02);
/* Disable clock buffer */
wcd_resmgr_codec_reg_update_bits(resmgr,
WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x00);
resmgr->clk_type = WCD_CLK_RCO; resmgr->clk_type = WCD_CLK_RCO;
} else { } else {
wcd_resmgr_codec_reg_update_bits(resmgr, wcd_resmgr_codec_reg_update_bits(resmgr,