usb: phy: Make cfg_ahb_clk optional

USB qusb2 and ssusb qmp phy drivers are not required to
manage gcc_usb_phy_cfg_ahb2phy_clk clock. It will stay
always ON except when in XO-shutdown. RPM will manage
this clock.

Change-Id: I92647d8ba53bb498b1048ea920a25c04441f6e10
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>

Documentation/devicetree/bindings/usb/msm-phy.txt

@@ -101,6 +101,10 @@ Required properties:
    Required "supply-name" examples are:
 	"vdd" : vdd supply for SSPHY digital circuit operation
 	"core" : high-voltage analog supply for SSPHY
+ - clocks: a list of phandles to the PHY clocks. Use as per
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+   property. Required clocks are "aux_clk" and "pipe_clk".
  - qcom,vdd-voltage-level: This property must be a list of three integer
    values (no, min, max) where each value represents either a voltage in
    microvolts or a value corresponding to voltage corner
@@ -119,6 +123,10 @@ Optional properties:
  - reg: Additional register set of address and length to control QMP PHY are:
    "tcsr_usb3_dp_phymode" : top-level CSR register to be written to select
    super speed usb qmp phy.
+ - clocks: a list of phandles to the PHY clocks. Use as per
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+   property. Required clocks are "cfg_ahb_clk", "phy_reset" and "phy_phy_reset".
  - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
    the USB PHY and the controller must rely on external VBUS notification in
    order to manually relay the notification to the SSPHY.
@@ -138,6 +146,17 @@ Example:
 		vdda18-supply = <&pmd9635_l8>;
 		qcom,vdd-voltage-level = <0 900000 1050000>;
 		qcom,vbus-valid-override;
+
+		clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
+			 <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
+			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
+			 <&clock_gcc clk_gcc_usb3_phy_reset>,
+			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,
+			 <&clock_gcc clk_ln_bb_clk1>,
+			 <&clock_gcc clk_gcc_usb3_clkref_clk>;
+
+		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
+			      "phy_phy_reset", "ref_clk_src", "ref_clk";
 	};
 
 QUSB2 High-Speed PHY
@@ -157,7 +176,7 @@ Required properties:
  - clocks: a list of phandles to the PHY clocks. Use as per
    Documentation/devicetree/bindings/clock/clock-bindings.txt
  - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
-   property. Required clocks are "cfg_ahb_clk" and "phy_reset".
+   property. Required clock is "phy_reset".
  - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
 
 Optional properties:
@@ -171,6 +190,10 @@ Optional properties:
    allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w
    control in device mode. The reg-names property is required if the
    reg property is specified.
+ - clocks: a list of phandles to the PHY clocks. Use as per
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+   property. "cfg_ahb_clk", "ref_clk_src" and "ref_clk" are optional clocks.
  - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
  - qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
  - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.

drivers/usb/phy/phy-msm-qusb-v2.c

@@ -767,9 +767,17 @@ static int qusb_phy_probe(struct platform_device *pdev)
 	else
 		clk_set_rate(qphy->ref_clk, 19200000);
 
-	qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
-	if (IS_ERR(qphy->cfg_ahb_clk))
-		return PTR_ERR(qphy->cfg_ahb_clk);
+	if (of_property_match_string(pdev->dev.of_node,
+				"clock-names", "cfg_ahb_clk") >= 0) {
+		qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
+		if (IS_ERR(qphy->cfg_ahb_clk)) {
+			ret = PTR_ERR(qphy->cfg_ahb_clk);
+			if (ret != -EPROBE_DEFER)
+				dev_err(dev,
+				"clk get failed for cfg_ahb_clk ret %d\n", ret);
+			return ret;
+		}
+	}
 
 	qphy->phy_reset = devm_clk_get(dev, "phy_reset");
 	if (IS_ERR(qphy->phy_reset))

drivers/usb/phy/phy-msm-ssusb-qmp.c

@@ -547,13 +547,16 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
 
 	clk_set_rate(phy->aux_clk, clk_round_rate(phy->aux_clk, ULONG_MAX));
 
-	phy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
-	if (IS_ERR(phy->cfg_ahb_clk)) {
-		ret = PTR_ERR(phy->cfg_ahb_clk);
-		phy->cfg_ahb_clk = NULL;
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to get cfg_ahb_clk\n");
-		goto err;
+	if (of_property_match_string(pdev->dev.of_node,
+				"clock-names", "cfg_ahb_clk") >= 0) {
+		phy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
+		if (IS_ERR(phy->cfg_ahb_clk)) {
+			ret = PTR_ERR(phy->cfg_ahb_clk);
+			if (ret != -EPROBE_DEFER)
+				dev_err(dev,
+				"failed to get cfg_ahb_clk ret %d\n", ret);
+			goto err;
+		}
 	}
 
 	phy->pipe_clk = devm_clk_get(dev, "pipe_clk");