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ARM: dts: msm: correct CE clock setting for crypto driver on msm8996

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Correct CE clock setting for crypto drivers, core_clk_src should
link to voting clock; otherwise, ce1 clock is set to be only half
of 171M HZ during crypto operations.

Change-Id: I0d9e048381a83d4788bf4f700d788137b59bd368
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
This commit is contained in:
Zhen Kong 2016-03-04 17:45:31 -08:00 • committed by David Keitel
parent 397d4d4efc
commit 49f4491edc
1 changed files with 2 additions and 2 deletions
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4
arch/arm/boot/dts/qcom/msm8996.dtsi
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@ -2506,7 +2506,7 @@
<55 512 3936000 393600>; <55 512 3936000 393600>;
clock-names = "core_clk_src", "core_clk", clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk"; "iface_clk", "bus_clk";
clocks = <&clock_gcc clk_ce1_clk>, clocks = <&clock_gcc clk_qcrypto_ce1_clk>,
<&clock_gcc clk_qcrypto_ce1_clk>, <&clock_gcc clk_qcrypto_ce1_clk>,
<&clock_gcc clk_gcc_ce1_ahb_m_clk>, <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
<&clock_gcc clk_gcc_ce1_axi_m_clk>; <&clock_gcc clk_gcc_ce1_axi_m_clk>;
@ -2536,7 +2536,7 @@
<55 512 3936000 393600>; <55 512 3936000 393600>;
clock-names = "core_clk_src", "core_clk", clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk"; "iface_clk", "bus_clk";
clocks = <&clock_gcc clk_ce1_clk>, clocks = <&clock_gcc clk_qcedev_ce1_clk>,
<&clock_gcc clk_qcedev_ce1_clk>, <&clock_gcc clk_qcedev_ce1_clk>,
<&clock_gcc clk_gcc_ce1_ahb_m_clk>, <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
<&clock_gcc clk_gcc_ce1_axi_m_clk>; <&clock_gcc clk_gcc_ce1_axi_m_clk>;