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clk: qcom: mdss: add DSI PLL clock driver support for msm8909

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Add changes for DSI PLL clock driver support for msm8909. Add
the compatibility string of the DSI PLL handle so that the
detection and support of DSI PLL driver for 8909 happens
dynamically.

Change-Id: If1fb96982433f90c5b82dda8686b7284825bcd09
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
This commit is contained in:
Shivaraj Shetty 2014-09-26 12:08:01 +05:30 • committed by David Keitel
parent 65de9c3fb4
commit 6e9b4cd96b
4 changed files with 18 additions and 3 deletions
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13
Documentation/devicetree/bindings/fb/mdss-pll.txt
View file

@ -5,12 +5,18 @@ are compatable with MIPI display serial interface specification,
HDMI and edp.
Required properties:
- compatible: Compatible name used in the driver
- compatible: Compatible name used in the driver. Should be one of:
"qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",
"qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",
"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994"
- cell-index: Specifies the controller used
- reg: offset and length of the register set for the device.
- reg-names : names to refer to register sets related to this device
- gdsc-supply: Phandle for gdsc regulator device node.
- vddio-supply: Phandle for vddio regulator device node.
- clocks: List of Phandles for clock device nodes
needed by the device.
- clock-names: List of clock names needed by the device.
- clock-rate: List of clock rates in Hz.
@ -36,7 +42,7 @@ Optional properties:
Example:
mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {
compatible = "qcom,mdss_dsi_pll";
compatible = "qcom,mdss_dsi_pll_8974";
label = "MDSS DSI 0 PLL";
cell-index = <0>;
@ -47,6 +53,9 @@ Example:
vddio-supply = <&pm8941_l12>;
vcca-supply = <&pm8941_l28>;
clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
<&clock_gcc clk_gcc_mdss_ahb_clk>,
<&clock_gcc clk_gcc_mdss_axi_clk>;
clock-names = "mdp_core_clk", "iface_clk", "bus_clk";
clock-rate = <0>, <0>, <0>;

3
drivers/clk/msm/mdss/mdss-dsi-pll-28lpm.c
View file

@ -286,7 +286,8 @@ int dsi_pll_clock_register_lpm(struct platform_device *pdev,
byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
if (pll_res->target_id == MDSS_PLL_TARGET_8916 ||
pll_res->target_id == MDSS_PLL_TARGET_8939) {
pll_res->target_id == MDSS_PLL_TARGET_8939 ||
pll_res->target_id == MDSS_PLL_TARGET_8909) {
rc = of_msm_clock_register(pdev->dev.of_node,
mdss_dsi_pllcc_8916, ARRAY_SIZE(mdss_dsi_pllcc_8916));
if (rc) {

4
drivers/clk/msm/mdss/mdss-pll.c
View file

@ -133,6 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8939")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
pll_res->target_id = MDSS_PLL_TARGET_8939;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8909")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
pll_res->target_id = MDSS_PLL_TARGET_8909;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8974")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_HPM;
pll_res->target_id = MDSS_PLL_TARGET_8974;
@ -365,6 +368,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
{.compatible = "qcom,mdss_hdmi_pll_8994"},
{.compatible = "qcom,mdss_dsi_pll_8916"},
{.compatible = "qcom,mdss_dsi_pll_8939"},
{.compatible = "qcom,mdss_dsi_pll_8909"},
{.compatible = "qcom,mdss_edp_pll"},
{.compatible = "qcom,mdss_hdmi_pll"},
{}

1
drivers/clk/msm/mdss/mdss-pll.h
View file

@ -42,6 +42,7 @@ enum {
MDSS_PLL_TARGET_8994,
MDSS_PLL_TARGET_8916,
MDSS_PLL_TARGET_8939,
MDSS_PLL_TARGET_8909,
};
struct mdss_pll_resources {