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ARM: dts: msm: Add LMH DCVSh interrupt information for msmcobalt

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Add information about the interrupt generated by the LMH DCVSh block for
msmcobalt.

This interrupt will be generated whenever the hardware makes a new
decision about the mitigation frequency.

Change-Id: I408fb7e62ef13b21dfea68bb6b878cdbeee411cd
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
This commit is contained in:
Ram Chandrasekar 2016-05-17 15:26:33 -06:00 • committed by Kyle Yan
parent 1884f6ccf9
commit 77fd5db7ee
1 changed files with 2 additions and 0 deletions
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2
arch/arm/boot/dts/qcom/msmcobalt.dtsi
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@ -2698,10 +2698,12 @@
&clock_cpu {
lmh_dcvs0: qcom,limits-dcvs@0 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
lmh_dcvs1: qcom,limits-dcvs@1 {
compatible = "qcom,msm-hw-limits";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};