evie/android_kernel_oneplus_msm8998
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ARM: dts: msm: Vote for BIMC GFX clock for SDM660 GPU

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Enable BIMC GFX clock when A512 GPU is ready to access data
from DDR on SDM660.

Change-Id: Ib76ef7a4fd5362f8cb972f1e4e070157a59c2c27
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
This commit is contained in:
Rajesh Kemisetti 2017-01-15 15:07:48 +05:30
parent 0236a0326d
commit a2434b9ba0
1 changed files with 5 additions and 4 deletions
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9
arch/arm/boot/dts/qcom/sdm660-gpu.dtsi
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@ -65,6 +65,7 @@
/* <HZ/12> */ /* <HZ/12> */
qcom,idle-timeout = <80>; qcom,idle-timeout = <80>;
qcom,no-nap;
qcom,highest-bank-bit = <14>; qcom,highest-bank-bit = <14>;
@ -75,11 +76,11 @@
<&clock_gcc GCC_GPU_CFG_AHB_CLK>, <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gfx GPUCC_RBBMTIMER_CLK>, <&clock_gfx GPUCC_RBBMTIMER_CLK>,
<&clock_gcc GCC_GPU_BIMC_GFX_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
<&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>, <&clock_gcc GCC_BIMC_GFX_CLK>,
<&clock_gpu GPUCC_RBCPR_CLK>; <&clock_gpu GPUCC_RBCPR_CLK>;
clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
"mem_clk", "mem_iface_clk", "rbcpr_clk"; "mem_clk", "alt_mem_iface_clk", "rbcpr_clk";
/* Bus Scale Settings */ /* Bus Scale Settings */
qcom,gpubw-dev = <&gpubw>; qcom,gpubw-dev = <&gpubw>;
@ -248,9 +249,9 @@
clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gcc GCC_GPU_BIMC_GFX_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
<&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>; <&clock_gcc GCC_BIMC_GFX_CLK>;
clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk";
qcom,secure_align_mask = <0xfff>; qcom,secure_align_mask = <0xfff>;
qcom,retention; qcom,retention;