evie/android_kernel_oneplus_msm8998
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usb: qmp: phy: Make sure QMP PHY reset write is completed

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Add explicit memory barrier after programming USB3_PHY_SW_RESET
register which makes sure that above write is not cached. If
this register write is cached, then phy driver is timing out
with checking PCS status. In some cases, L2 cache memory error
is seen when that register write is flushed whereas usb phy
clock is turned off.

CRs-Fixed: 990963
Change-Id: Iebe8cb4034721e76fa5ea63e33304b9dc0243797
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
This commit is contained in:
Mayank Rana 2016-03-29 11:11:28 -07:00 • committed by Jeevan Shriram
parent 1431dc8179
commit b1c51424b1
1 changed files with 4 additions and 1 deletions
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5
drivers/usb/phy/phy-msm-ssusb-qmp.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and * it under the terms of the GNU General Public License version 2 and
@ -274,6 +274,9 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy)
writel_relaxed(0x03, phy->base + phy->phy_reg[USB3_PHY_START]); writel_relaxed(0x03, phy->base + phy->phy_reg[USB3_PHY_START]);
writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]); writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]);
/* Make sure above write completed to bring PHY out of reset */
mb();
/* Wait for PHY initialization to be done */ /* Wait for PHY initialization to be done */
do { do {
if (readl_relaxed(phy->base + if (readl_relaxed(phy->base +