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iommu/arm-smmu: do a single 64-bit write for ATOS

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Hardware requires that the ATOS command be issued with a single 64-bit
write instead of two 32-bit writes as we're currently doing.  Fix this.

Change-Id: I43104c89c2f27b75d1176c8cbcd214666321244f
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This commit is contained in:
Mitchel Humpherys 2014-12-04 12:11:44 -08:00 • committed by David Keitel
parent 7c0f5ca1da
commit c1a40a76ec
1 changed files with 2 additions and 4 deletions
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6
drivers/iommu/arm-smmu.c
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@ -1902,10 +1902,8 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
u32 reg = iova & ~0xfff; u32 reg = iova & ~0xfff;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
} else { } else {
u32 reg = iova & ~0xfff; u64 reg = iova & ~0xfff;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); writeq_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
reg = (iova & ~0xfff) >> 32;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
} }
if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp, if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,