evie/android_kernel_oneplus_msm8998
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msm: camera: Enable ov2685 on msm8937

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Changing csiphy clock lane setting and removing a
register write in combo mode to enable ov2685 on
msm8937.

Change-Id: I8e6d987a8072a0c2679f7b53bfd3522b8dfa5297
Signed-off-by: Vijay kumar Tumati <vtumati@codeaurora.org>
This commit is contained in:
Vijay kumar Tumati 2015-12-02 16:28:28 +05:30 • committed by David Keitel
parent ab75fe5eea
commit ca20ea97a9
4 changed files with 7 additions and 3 deletions
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1
drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_4_2_hwreg.h
View file

@ -22,6 +22,7 @@ struct csiphy_reg_parms_t csiphy_v3_4_2 = {
.mipi_csiphy_interrupt_status0_addr = 0x8B0,
.mipi_csiphy_interrupt_clear0_addr = 0x858,
.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.combo_clk_mask = 0x10,
};
struct csiphy_reg_3ph_parms_t csiphy_v3_4_2_3ph = {

1
drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h
View file

@ -22,6 +22,7 @@ struct csiphy_reg_parms_t csiphy_v3_5 = {
.mipi_csiphy_interrupt_status0_addr = 0x8B0,
.mipi_csiphy_interrupt_clear0_addr = 0x858,
.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.combo_clk_mask = 0x8,
};
struct csiphy_reg_3ph_parms_t csiphy_v3_5_3ph = {

7
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
View file

@ -332,8 +332,8 @@ static int msm_csiphy_2phase_lane_config(
if (csiphy_params->combo_mode == 1) {
val |= 0xA;
if (mask == 0x8) {
/* lane 6 is second clock lane for combo mode */
if (mask == csiphy_dev->ctrl_reg->
csiphy_reg.combo_clk_mask) {
val |= 0x4;
clk_lane = 1;
}
@ -422,7 +422,8 @@ static int msm_csiphy_2phase_lane_config(
}
mask <<= 1;
}
if (csiphy_dev->hw_version == CSIPHY_VERSION_V342) {
if (csiphy_dev->hw_version == CSIPHY_VERSION_V342 &&
csiphy_params->combo_mode != 1) {
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl0.data,
csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

1
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
View file

@ -56,6 +56,7 @@ struct csiphy_reg_parms_t {
uint32_t mipi_csiphy_glbl_t_init_cfg0_addr;
uint32_t mipi_csiphy_t_wakeup_cfg0_addr;
uint32_t csiphy_version;
uint32_t combo_clk_mask;
};
struct csiphy_reg_3ph_parms_t {