evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

iommu/arm-smmu: add and use definitions for the TTBCR2.SEP field

Browse source 
Currently we're repurposing the definitions used for the TTBCR2.PASize
field for TTBCR2.SEP since they conveniently have the same values.
However, this might look like a bug at first glance to the casual
passer-by, appearing that we're using the wrong bit definitions for the
field.  For example, we're using TTBCR2_ADDR_32 to indicate that the
Sign Extension Bit should live at 31 (not 32 as the name of the macro
might imply).  Reduce cumulative human cognitive load by adding some
definitions specifically for the SEP field.

Change-Id: Ia406951499453e2badca42a1cc4cdbc566af4dab
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
This commit is contained in:
Mitchel Humpherys 2014-11-04 10:40:00 -08:00 • committed by David Keitel
parent b1dea0183f
commit cc4f1763f0
1 changed files with 13 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
drivers/iommu/arm-smmu.c
View file

@ -309,6 +309,13 @@
#define TTBCR2_ADDR_44 4 #define TTBCR2_ADDR_44 4
#define TTBCR2_ADDR_48 5 #define TTBCR2_ADDR_48 5
#define TTBCR2_SEP_31 0
#define TTBCR2_SEP_35 1
#define TTBCR2_SEP_39 2
#define TTBCR2_SEP_41 3
#define TTBCR2_SEP_43 4
#define TTBCR2_SEP_47 5
#define TTBRn_HI_ASID_SHIFT 16 #define TTBRn_HI_ASID_SHIFT 16
#define MAIR_ATTR_SHIFT(n) ((n) << 3) #define MAIR_ATTR_SHIFT(n) ((n) << 3)
@ -940,23 +947,23 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
/* TTBCR2 */ /* TTBCR2 */
switch (smmu->s1_input_size) { switch (smmu->s1_input_size) {
case 32: case 32:
reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_31 << TTBCR2_SEP_SHIFT);
break; break;
case 36: case 36:
reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_35 << TTBCR2_SEP_SHIFT);
break; break;
case 39: case 39:
case 40: case 40:
reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_39 << TTBCR2_SEP_SHIFT);
break; break;
case 42: case 42:
reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_41 << TTBCR2_SEP_SHIFT);
break; break;
case 44: case 44:
reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_43 << TTBCR2_SEP_SHIFT);
break; break;
case 48: case 48:
reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); reg = (TTBCR2_SEP_47 << TTBCR2_SEP_SHIFT);
break; break;
} }