evie/android_kernel_oneplus_msm8998
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clk: msm: mdss: update the programming of DYNAMIC_REFRESH_PLL_UPPER_ADDR2

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As part of dynamic refresh sequence, we program PLL_UPPER_ADDR2 register to
0x003FFE00 instead of 0x001FFE00. This causes a register write to
DSIPHY_PLL_KVCO_COUNT1 to 0x1 during the dynamic refresh operation whereas
the register write is supposed to happen for DSIPHY_CMN_PLL_CNTRL register.
Update the write value to DYNAMIC_REFRESH_PLL_UPPER_ADDR2 to take care
of this.

Change-Id: I991920d5a45e79670a4a033c8a83bef6c7f3136b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2016-02-25 14:16:27 +05:30 • committed by David Keitel
parent dcb0035091
commit ce96391696
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
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@ -909,7 +909,7 @@ static void shadow_pll_dynamic_refresh_8996(struct mdss_pll_resources *pll,
MDSS_PLL_REG_W(pll->dyn_pll_base,
DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0000001E);
MDSS_PLL_REG_W(pll->dyn_pll_base,
DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x003FFE00);
DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x001FFE00);
/*
* Ensure all the dynamic refresh registers are written before