Merge "ARM: dts: msm: Add GPU coresight properties for msm8998"
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commit
cfd61208ea
5 changed files with 31 additions and 1 deletions
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@ -187,7 +187,7 @@ Documentation/devicetree/bindings/coresight/coresight.txt
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- coresight-child-list List of phandles pointing to the children of this
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- coresight-child-list List of phandles pointing to the children of this
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component.
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component.
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- coresight-child-ports List of input port numbers of the children.
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- coresight-child-ports List of input port numbers of the children.
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- coresight-atid The unique ATID value of the coresight device
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Example of A330 GPU in MSM8916:
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Example of A330 GPU in MSM8916:
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@ -277,6 +277,14 @@
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<&funnel_apss_merg_out_funnel_in1>;
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<&funnel_apss_merg_out_funnel_in1>;
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};
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};
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};
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};
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port@6 {
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reg = <7>;
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funnel_in1_in_gfx: endpoint {
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slave-mode;
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remote-endpoint =
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<&gfx_out_funnel_in1>;
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};
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};
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};
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};
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};
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};
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@ -122,6 +122,14 @@
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vddcx-supply = <&gdsc_gpu_cx>;
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vddcx-supply = <&gdsc_gpu_cx>;
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vdd-supply = <&gdsc_gpu_gx>;
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vdd-supply = <&gdsc_gpu_gx>;
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/* Trace bus */
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coresight-name = "coresight-gfx";
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port {
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gfx_out_funnel_in1: endpoint {
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remote-endpoint = <&funnel_in1_in_gfx>;
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};
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};
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/* GPU Mempools */
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/* GPU Mempools */
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qcom,gpu-mempools {
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qcom,gpu-mempools {
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#address-cells= <1>;
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#address-cells= <1>;
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@ -676,11 +676,13 @@ ssize_t adreno_coresight_store_register(struct device *dev,
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* @registers - Array of GPU specific registers to configure trace bus output
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* @registers - Array of GPU specific registers to configure trace bus output
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* @count - Number of registers in the array
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* @count - Number of registers in the array
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* @groups - Pointer to an attribute list of control files
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* @groups - Pointer to an attribute list of control files
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* @atid - The unique ATID value of the coresight device
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*/
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*/
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struct adreno_coresight {
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struct adreno_coresight {
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struct adreno_coresight_register *registers;
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struct adreno_coresight_register *registers;
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unsigned int count;
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unsigned int count;
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const struct attribute_group **groups;
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const struct attribute_group **groups;
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unsigned int atid;
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};
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};
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@ -200,6 +200,9 @@ static int _adreno_coresight_set(struct adreno_device *adreno_dev)
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kgsl_regwrite(device, coresight->registers[i].offset,
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kgsl_regwrite(device, coresight->registers[i].offset,
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coresight->registers[i].value);
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coresight->registers[i].value);
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kgsl_property_read_u32(device, "coresight-atid",
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(unsigned int *)&(coresight->atid));
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return 0;
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return 0;
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}
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}
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/**
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/**
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@ -281,7 +284,16 @@ void adreno_coresight_start(struct adreno_device *adreno_dev)
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_adreno_coresight_set(adreno_dev);
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_adreno_coresight_set(adreno_dev);
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}
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}
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static int adreno_coresight_trace_id(struct coresight_device *csdev)
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{
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struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent);
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struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(ADRENO_DEVICE(device));
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return gpudev->coresight->atid;
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}
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static const struct coresight_ops_source adreno_coresight_source_ops = {
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static const struct coresight_ops_source adreno_coresight_source_ops = {
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.trace_id = adreno_coresight_trace_id,
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.enable = adreno_coresight_enable,
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.enable = adreno_coresight_enable,
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.disable = adreno_coresight_disable,
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.disable = adreno_coresight_disable,
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};
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};
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