Merge "ARM: dts: msm: Add GPU coresight properties for msm8998"

This commit is contained in:
Linux Build Service Account 2016-12-09 19:59:21 -08:00 committed by Gerrit - the friendly Code Review server
commit cfd61208ea
5 changed files with 31 additions and 1 deletions

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@ -187,7 +187,7 @@ Documentation/devicetree/bindings/coresight/coresight.txt
- coresight-child-list List of phandles pointing to the children of this - coresight-child-list List of phandles pointing to the children of this
component. component.
- coresight-child-ports List of input port numbers of the children. - coresight-child-ports List of input port numbers of the children.
- coresight-atid The unique ATID value of the coresight device
Example of A330 GPU in MSM8916: Example of A330 GPU in MSM8916:

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@ -277,6 +277,14 @@
<&funnel_apss_merg_out_funnel_in1>; <&funnel_apss_merg_out_funnel_in1>;
}; };
}; };
port@6 {
reg = <7>;
funnel_in1_in_gfx: endpoint {
slave-mode;
remote-endpoint =
<&gfx_out_funnel_in1>;
};
};
}; };
}; };

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@ -122,6 +122,14 @@
vddcx-supply = <&gdsc_gpu_cx>; vddcx-supply = <&gdsc_gpu_cx>;
vdd-supply = <&gdsc_gpu_gx>; vdd-supply = <&gdsc_gpu_gx>;
/* Trace bus */
coresight-name = "coresight-gfx";
port {
gfx_out_funnel_in1: endpoint {
remote-endpoint = <&funnel_in1_in_gfx>;
};
};
/* GPU Mempools */ /* GPU Mempools */
qcom,gpu-mempools { qcom,gpu-mempools {
#address-cells= <1>; #address-cells= <1>;

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@ -676,11 +676,13 @@ ssize_t adreno_coresight_store_register(struct device *dev,
* @registers - Array of GPU specific registers to configure trace bus output * @registers - Array of GPU specific registers to configure trace bus output
* @count - Number of registers in the array * @count - Number of registers in the array
* @groups - Pointer to an attribute list of control files * @groups - Pointer to an attribute list of control files
* @atid - The unique ATID value of the coresight device
*/ */
struct adreno_coresight { struct adreno_coresight {
struct adreno_coresight_register *registers; struct adreno_coresight_register *registers;
unsigned int count; unsigned int count;
const struct attribute_group **groups; const struct attribute_group **groups;
unsigned int atid;
}; };

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@ -200,6 +200,9 @@ static int _adreno_coresight_set(struct adreno_device *adreno_dev)
kgsl_regwrite(device, coresight->registers[i].offset, kgsl_regwrite(device, coresight->registers[i].offset,
coresight->registers[i].value); coresight->registers[i].value);
kgsl_property_read_u32(device, "coresight-atid",
(unsigned int *)&(coresight->atid));
return 0; return 0;
} }
/** /**
@ -281,7 +284,16 @@ void adreno_coresight_start(struct adreno_device *adreno_dev)
_adreno_coresight_set(adreno_dev); _adreno_coresight_set(adreno_dev);
} }
static int adreno_coresight_trace_id(struct coresight_device *csdev)
{
struct kgsl_device *device = dev_get_drvdata(csdev->dev.parent);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(ADRENO_DEVICE(device));
return gpudev->coresight->atid;
}
static const struct coresight_ops_source adreno_coresight_source_ops = { static const struct coresight_ops_source adreno_coresight_source_ops = {
.trace_id = adreno_coresight_trace_id,
.enable = adreno_coresight_enable, .enable = adreno_coresight_enable,
.disable = adreno_coresight_disable, .disable = adreno_coresight_disable,
}; };