clk: msm: clock-gcc-cobalt: Add the cnoc_periph RPM resource support
Add support for modelling a new cnoc_periph RPM resource on MSM COBALT. In addition, fix the rpm_res_type being used for the mmssnoc_axi_clk and remove the pnoc resource support. CRs-Fixed: 1003213 Change-Id: I9f9845fea425fc4463dae72e8f8ab6e8bda23121 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda
Kyle Yan
parent
5c5c7ecab5
commit
d4c48266b2
4 changed files with 18 additions and 31 deletions
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@ -1945,17 +1945,16 @@
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clocks = <&clock_gcc clk_cxo_clk_src>,
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<&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
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<&clock_gcc clk_pnoc_clk>,
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<&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>,
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<&clock_gcc clk_gcc_boot_rom_ahb_clk>,
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<&clock_gcc clk_gpll0_out_msscc>,
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<&clock_gcc clk_gcc_mss_snoc_axi_clk>,
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<&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
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<&clock_gcc clk_qdss_clk>;
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clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
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clock-names = "xo", "iface_clk", "bus_clk",
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"mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
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"mnoc_axi_clk", "qdss_clk";
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qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
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qcom,proxy-clock-names = "xo", "qdss_clk";
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qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
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"gpll0_mss_clk", "snoc_axi_clk",
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"mnoc_axi_clk";
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@ -59,10 +59,13 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
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DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE,
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CXO_CLK_SRC_ID, 19200000);
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DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD(cnoc_periph_clk, cnoc_periph_a_clk, RPM_BUS_CLK_TYPE,
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CNOC_PERIPH_CLK_ID, NULL);
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static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, &cnoc_periph_a_clk.c,
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LONG_MAX);
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static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
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@ -91,17 +94,12 @@ DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk3_pin, ln_bb_clk3_pin_ao,
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LN_BB_CLK3_PIN_ID);
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static DEFINE_CLK_VOTER(mcd_ce1_clk, &ce1_clk.c, 85710000);
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DEFINE_CLK_DUMMY(measure_only_bimc_hmss_axi_clk, 0);
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DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk, RPM_BUS_CLK_TYPE,
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MMSSNOC_AXI_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk,
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RPM_MMAXI_CLK_TYPE, MMSSNOC_AXI_CLK_ID, NULL);
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DEFINE_CLK_RPM_SMD_BRANCH(aggre1_noc_clk, aggre1_noc_a_clk,
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RPM_AGGR_CLK_TYPE, AGGR1_NOC_ID, 1000);
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DEFINE_CLK_RPM_SMD_BRANCH(aggre2_noc_clk, aggre2_noc_a_clk,
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RPM_AGGR_CLK_TYPE, AGGR2_NOC_ID, 1000);
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static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(pnoc_pm_clk, &pnoc_clk.c, LONG_MAX);
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static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, 0);
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static DEFINE_CLK_VOTER(qcedev_ce1_clk, &ce1_clk.c, 85710000);
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static DEFINE_CLK_VOTER(qcrypto_ce1_clk, &ce1_clk.c, 85710000);
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DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE,
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@ -2468,14 +2466,15 @@ static struct mux_clk gcc_debug_mux = {
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static struct clk_lookup msm_clocks_rpm_cobalt[] = {
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CLK_LIST(cxo_clk_src),
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CLK_LIST(pnoc_clk),
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CLK_LIST(pnoc_a_clk),
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CLK_LIST(bimc_clk),
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CLK_LIST(bimc_a_clk),
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CLK_LIST(cnoc_clk),
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CLK_LIST(cnoc_a_clk),
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CLK_LIST(snoc_clk),
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CLK_LIST(snoc_a_clk),
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CLK_LIST(cnoc_periph_clk),
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CLK_LIST(cnoc_periph_a_clk),
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CLK_LIST(cnoc_periph_keepalive_a_clk),
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CLK_LIST(bimc_msmbus_clk),
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CLK_LIST(bimc_msmbus_a_clk),
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CLK_LIST(ce1_clk),
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@ -2517,11 +2516,6 @@ static struct clk_lookup msm_clocks_rpm_cobalt[] = {
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CLK_LIST(aggre1_noc_a_clk),
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CLK_LIST(aggre2_noc_clk),
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CLK_LIST(aggre2_noc_a_clk),
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CLK_LIST(pnoc_keepalive_a_clk),
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CLK_LIST(pnoc_msmbus_clk),
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CLK_LIST(pnoc_msmbus_a_clk),
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CLK_LIST(pnoc_pm_clk),
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CLK_LIST(pnoc_sps_clk),
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CLK_LIST(qcedev_ce1_clk),
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CLK_LIST(qcrypto_ce1_clk),
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CLK_LIST(qdss_clk),
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@ -2797,11 +2791,9 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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/*
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* Hold an active set vote for the PNOC AHB source. Sleep set vote is 0.
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*/
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clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
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clk_prepare_enable(&pnoc_keepalive_a_clk.c);
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/* Hold an active set vote for the cnoc_periph resource */
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clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
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clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);
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/* This clock is used for all MMSSCC register access */
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clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c);
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@ -19,14 +19,15 @@
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#define clk_ce1_clk 0x42229c55
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#define clk_ce1_a_clk 0x44a833fe
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#define clk_cxo_clk_src 0x79e95308
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#define clk_pnoc_clk 0x4325d220
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#define clk_pnoc_a_clk 0x2808c12b
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#define clk_bimc_clk 0x4b80bf00
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#define clk_bimc_a_clk 0x4b25668a
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#define clk_cnoc_clk 0xd5ccb7f4
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#define clk_cnoc_a_clk 0xd8fe2ccc
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#define clk_snoc_clk 0x2c341aa0
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#define clk_snoc_a_clk 0x8fcef2af
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#define clk_cnoc_periph_clk 0xb11e9cf9
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#define clk_cnoc_periph_a_clk 0x1d7faa2e
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#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2
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#define clk_ln_bb_clk1 0xb867b147
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#define clk_ln_bb_clk1_ao 0x7f63a93a
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#define clk_ln_bb_clk1_pin 0x6fc5653c
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@ -61,11 +62,6 @@
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#define clk_mcd_ce1_clk 0xbb615d26
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#define clk_mmssnoc_axi_clk 0xdb4b31e6
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#define clk_mmssnoc_axi_a_clk 0xd4970614
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#define clk_pnoc_keepalive_a_clk 0xf8f91f0b
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#define clk_pnoc_msmbus_clk 0x38b95c77
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#define clk_pnoc_msmbus_a_clk 0x8c9b4e93
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#define clk_pnoc_pm_clk 0xd6f7dfb9
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#define clk_pnoc_sps_clk 0xd482ecc7
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#define clk_qcedev_ce1_clk 0x293f97b0
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#define clk_qcrypto_ce1_clk 0xa6ac14df
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#define clk_qdss_clk 0x1492202a
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@ -30,9 +30,9 @@
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#define CXO_CLK_SRC_ID 0x0
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#define QDSS_CLK_ID 0x1
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#define PNOC_CLK_ID 0x0
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#define SNOC_CLK_ID 0x1
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#define CNOC_CLK_ID 0x2
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#define CNOC_PERIPH_CLK_ID 0x0
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#define BIMC_CLK_ID 0x0
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#define IPA_CLK_ID 0x0
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#define CE1_CLK_ID 0x0
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