mmc: core: set REL_WR_SEC_C register to 0x1 per eMMC5.0 spec
Some eMMC vendors violate eMMC 5.0 spec and set REL_WR_SEC_C register to 0x10 to indicate the ability of RPMB throughput improvement thus lead to failure when TZ module write data to RPMB partition. This change will check bit[4] of EXT_CSD[166] and if it is not set then change value of REL_WR_SEC_C to 0x1 directly ignoring value of EXT_CSD[222]. CRs-Fixed: 866059 Change-Id: Ibd12c94ad691eca1fa3ea2049b750a6e98178678 Signed-off-by: xiaonian <xiaonian@codeaurora.org> Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
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@ -563,6 +563,19 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
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card->ext_csd.rel_param = ext_csd[EXT_CSD_WR_REL_PARAM];
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card->ext_csd.rst_n_function = ext_csd[EXT_CSD_RST_N_FUNCTION];
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/*
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* Some eMMC vendors violate eMMC 5.0 spec and set
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* REL_WR_SEC_C register to 0x10 to indicate the
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* ability of RPMB throughput improvement thus lead
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* to failure when TZ module write data to RPMB
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* partition. So check bit[4] of EXT_CSD[166] and
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* if it is not set then change value of REL_WR_SEC_C
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* to 0x1 directly ignoring value of EXT_CSD[222].
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*/
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if (!(card->ext_csd.rel_param &
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EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR))
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card->ext_csd.rel_sectors = 0x1;
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/*
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* RPMB regions are defined in multiples of 128K.
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*/
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