evie/android_kernel_oneplus_msm8998
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msm: pcie: slow down PCIe PHY RX clock for SVS mode

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In order for PCIe to reliabily work in SVS mode,
the PCIe PHY RX clock needs to be slowed.

Change-Id: Ic6edf487011ef4ac71d486210b1f6176e2142551
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2015-07-13 14:46:13 -07:00 • committed by David Keitel
parent e2c14b7033
commit e4c1b74bb9
1 changed files with 4 additions and 0 deletions
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4
drivers/pci/host/pci-msm.c
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@ -117,6 +117,7 @@
#define QSERDES_RX_N_SIGDET_ENABLES(n, m) (RX(n, m) + 0x110)
#define QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(n, m) (RX(n, m) + 0x11C)
#define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118)
#define QSERDES_RX_N_RX_BAND(n, m) (RX(n, m) + 0x120)
#define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00)
#define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04)
@ -1178,6 +1179,9 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)
msm_pcie_write_reg(dev->phy,
QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy),
0xDB);
msm_pcie_write_reg(dev->phy,
QSERDES_RX_N_RX_BAND(dev->rc_idx, common_phy),
0x18);
msm_pcie_write_reg(dev->phy,
QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy),
0x04);