ARM: dts: msm: specify I2C configuration for msmfalcon
Initial support for all BLSP I2Cs with default configuration and disabled state such that clients can overwrite and enable respective I2C instance as per need. Change-Id: If08ff46e72d537254e90707f28c849a86f262853 Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
This commit is contained in:
Mukesh Kumar Savaliya
parent
abcf426a00
commit
e75b50d38f
3 changed files with 433 additions and 0 deletions
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@ -22,11 +22,203 @@
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spi6 = &spi_6;
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spi7 = &spi_7;
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spi8 = &spi_8;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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i2c7 = &i2c_7;
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i2c8 = &i2c_8;
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};
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};
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&soc {
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i2c_1: i2c@c175000 { /* BLSP1 QUP1 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc175000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 95 0>;
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dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
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<&dma_blsp1 5 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_1_active>;
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pinctrl-1 = <&i2c_1_sleep>;
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status = "disabled";
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};
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i2c_2: i2c@c176000 { /* BLSP1 QUP2 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc176000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 96 0>;
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dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
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<&dma_blsp1 7 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_2_active>;
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pinctrl-1 = <&i2c_2_sleep>;
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status = "disabled";
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};
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i2c_3: i2c@c177000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc177000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 97 0>;
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dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
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<&dma_blsp1 9 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_3_active>;
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pinctrl-1 = <&i2c_3_sleep>;
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status = "disabled";
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};
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i2c_4: i2c@c178000 { /* BLSP1 QUP4 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc178000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 98 0>;
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dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
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<&dma_blsp1 11 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <86>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_4_active>;
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pinctrl-1 = <&i2c_4_sleep>;
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status = "disabled";
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};
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i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc1b5000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 101 0>;
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dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
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<&dma_blsp2 5 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <84>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_5_active>;
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pinctrl-1 = <&i2c_5_sleep>;
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status = "disabled";
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};
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i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc1b6000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 102 0>;
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dmas = <&dma_blsp2 6 64 0x20000020 0x20>,
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<&dma_blsp2 7 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <84>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_6_active>;
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pinctrl-1 = <&i2c_6_sleep>;
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status = "disabled";
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};
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i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc1b7000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 103 0>;
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dmas = <&dma_blsp2 8 64 0x20000020 0x20>,
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<&dma_blsp2 9 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <84>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_7_active>;
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pinctrl-1 = <&i2c_7_sleep>;
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status = "disabled";
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};
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i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc1b8000 0x600>;
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reg-names = "qup_phys_addr";
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interrupt-names = "qup_irq";
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interrupts = <0 104 0>;
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dmas = <&dma_blsp2 10 64 0x20000020 0x20>,
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<&dma_blsp2 11 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <84>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_8_active>;
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pinctrl-1 = <&i2c_8_sleep>;
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status = "disabled";
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};
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spi_1: spi@c175000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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@ -113,6 +113,231 @@
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};
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};
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/* I2C CONFIGURATION */
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i2c_1 {
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i2c_1_active: i2c_1_active {
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mux {
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pins = "gpio2", "gpio3";
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function = "blsp_i2c1";
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};
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config {
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pins = "gpio2", "gpio3";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_1_sleep: i2c_1_sleep {
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mux {
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pins = "gpio2", "gpio3";
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function = "blsp_i2c1";
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};
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config {
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pins = "gpio2", "gpio3";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_2 {
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i2c_2_active: i2c_2_active {
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mux {
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pins = "gpio6", "gpio7";
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function = "blsp_i2c2";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_2_sleep: i2c_2_sleep {
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mux {
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pins = "gpio6", "gpio7";
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function = "blsp_i2c2";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_3 {
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i2c_3_active: i2c_3_active {
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mux {
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pins = "gpio10", "gpio11";
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function = "blsp_i2c3";
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};
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config {
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pins = "gpio10", "gpio11";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_3_sleep: i2c_3_sleep {
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mux {
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pins = "gpio10", "gpio11";
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function = "blsp_i2c3";
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};
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config {
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pins = "gpio10", "gpio11";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_4 {
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i2c_4_active: i2c_4_active {
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mux {
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pins = "gpio14", "gpio15";
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function = "blsp_i2c4";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_4_sleep: i2c_4_sleep {
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mux {
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pins = "gpio14", "gpio15";
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function = "blsp_i2c4";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_5 {
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i2c_5_active: i2c_5_active {
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mux {
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pins = "gpio18", "gpio19";
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function = "blsp_i2c5";
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};
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config {
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pins = "gpio18", "gpio19";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_5_sleep: i2c_5_sleep {
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mux {
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pins = "gpio18", "gpio19";
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function = "blsp_i2c5";
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};
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config {
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pins = "gpio18", "gpio19";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_6 {
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i2c_6_active: i2c_6_active {
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mux {
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pins = "gpio22", "gpio23";
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function = "blsp_i2c6";
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};
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config {
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pins = "gpio22", "gpio23";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_6_sleep: i2c_6_sleep {
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mux {
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pins = "gpio22", "gpio23";
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function = "blsp_i2c6";
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};
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config {
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pins = "gpio22", "gpio23";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_7 {
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i2c_7_active: i2c_7_active {
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mux {
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pins = "gpio26", "gpio27";
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function = "blsp_i2c7";
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};
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config {
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pins = "gpio26", "gpio27";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_7_sleep: i2c_7_sleep {
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mux {
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pins = "gpio26", "gpio27";
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function = "blsp_i2c7";
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};
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config {
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pins = "gpio26", "gpio27";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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i2c_8 {
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i2c_8_active: i2c_8_active {
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mux {
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pins = "gpio30", "gpio31";
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function = "blsp_i2c8_a";
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};
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config {
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pins = "gpio30", "gpio31";
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drive-strength = <2>;
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bias-disable;
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};
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};
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i2c_8_sleep: i2c_8_sleep {
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mux {
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pins = "gpio30", "gpio31";
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function = "blsp_i2c8_a";
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};
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config {
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pins = "gpio30", "gpio31";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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/* SPI CONFIGURATION */
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spi_1 {
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spi_1_active: spi_1_active {
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@ -249,6 +249,22 @@
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clock-frequency = <19200000>;
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};
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dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0xc144000 0x1F000>;
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interrupts = <0 238 0>;
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qcom,summing-threshold = <0x10>;
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};
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dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0xc184000 0x1F000>;
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interrupts = <0 239 0>;
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qcom,summing-threshold = <0x10>;
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};
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spmi_bus: qcom,spmi@800f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x800f000 0x1000>,
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|
|||
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Reference in a new issue