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Merge "ARM: dts: msm: Update camera clock sources for sdm630"

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Linux Build Service Account 2017-04-05 04:05:35 -07:00 • committed by Gerrit - the friendly Code Review server
commit e81f37a9e5
1 changed files with 10 additions and 10 deletions
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20
arch/arm/boot/dts/qcom/sdm630-camera.dtsi
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@ -54,8 +54,8 @@
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
"csiphy_ahb2crif"; "csiphy_ahb2crif";
qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
0 384000000 0 0>; 0 200000000 0 0>;
status = "ok"; status = "ok";
}; };
@ -92,8 +92,8 @@
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
"csiphy_ahb2crif"; "csiphy_ahb2crif";
qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
0 384000000 0 0>; 0 200000000 0 0>;
status = "ok"; status = "ok";
}; };
@ -130,8 +130,8 @@
"csiphy_timer_src_clk", "csiphy_timer_clk", "csiphy_timer_src_clk", "csiphy_timer_clk",
"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
"csiphy_ahb2crif"; "csiphy_ahb2crif";
qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
0 384000000 0 0>; 0 200000000 0 0>;
status = "ok"; status = "ok";
}; };
@ -171,7 +171,7 @@
"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
"csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "cphy_csid_clk"; "csi_pix_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
0 0 0 0 0>; 0 0 0 0 0>;
status = "ok"; status = "ok";
}; };
@ -212,7 +212,7 @@
"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
"csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "cphy_csid_clk"; "csi_pix_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
0 0 0 0 0>; 0 0 0 0 0>;
status = "ok"; status = "ok";
}; };
@ -253,7 +253,7 @@
"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
"csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "cphy_csid_clk"; "csi_pix_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
0 0 0 0 0>; 0 0 0 0 0>;
status = "ok"; status = "ok";
}; };
@ -294,7 +294,7 @@
"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
"csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "cphy_csid_clk"; "csi_pix_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
0 0 0 0 0>; 0 0 0 0 0>;
status = "ok"; status = "ok";
}; };