ARM: dts: msm: put ipa3 in smmu s1-bypass on msmcobalt
Enable SMMU on IPA3 and put in stage1-bypass mode to not do the memory mapping. Change-Id: Id2811c67a423c82201993b3119647a3d4caf4517 Acked-by: Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
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1 changed files with 23 additions and 2 deletions
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@ -966,8 +966,12 @@
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qcom,do-not-use-ch-gsi-20;
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qcom,ipa-wdi2;
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qcom,use-64-bit-dma-mask;
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clock-names = "core_clk";
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clocks = <&clock_gcc clk_ipa_clk>;
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clocks = <&clock_gcc clk_ipa_clk>,
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<&clock_gcc clk_aggre2_noc_clk>;
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clock-names = "core_clk", "smmu_clk";
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qcom,arm-smmu;
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qcom,smmu-disable-htw;
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qcom,smmu-s1-bypass;
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qcom,msm-bus,name = "ipa";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <3>;
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@ -1074,6 +1078,23 @@
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compatible = "qcom,smp2pgpio-map-ipa-1-in";
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gpios = <&smp2pgpio_ipa_1_in 0 0>;
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};
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ipa_smmu_ap: ipa_smmu_ap {
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compatible = "qcom,ipa-smmu-ap-cb";
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iommus = <&anoc2_smmu 0x18e0>;
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qcom,iova-mapping = <0x10000000 0x40000000>;
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};
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ipa_smmu_wlan: ipa_smmu_wlan {
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compatible = "qcom,ipa-smmu-wlan-cb";
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iommus = <&anoc2_smmu 0x18e1>;
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};
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ipa_smmu_uc: ipa_smmu_uc {
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compatible = "qcom,ipa-smmu-uc-cb";
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iommus = <&anoc2_smmu 0x18e2>;
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qcom,iova-mapping = <0x40000000 0x20000000>;
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};
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};
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qcom,ipa_fws@1e08000 {
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