ARM: dts: msm: Add blsp instances for 8996
Add i2c, uart and spi instances for 8996. Change-Id: I5262dd0ef9fee8d4f6ae7bed2bc2edc2d8a9e71b Signed-off-by: Ankit Gupta <ankgupta@codeaurora.org> Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
This commit is contained in:
Ankit Gupta
David Keitel
parent
dd68fb8d5b
commit
f571ff2a0b
3 changed files with 326 additions and 0 deletions
174
arch/arm/boot/dts/qcom/msm8996-blsp.dtsi
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174
arch/arm/boot/dts/qcom/msm8996-blsp.dtsi
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@ -0,0 +1,174 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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aliases {
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spi9 = &spi_9;
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spi10 = &spi_10;
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spi12 = &spi_12;
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};
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};
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&soc {
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blsp1_uart3: uart@7571000 { /* BLSP1 UART3 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x7571000 0x200>,
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<0x7544000 0x2b000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart3>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 109 0
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1 &intc 0 238 0
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2 &tlmm 42 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <4>;
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qcom,bam-rx-ep-pipe-index = <5>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
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<&clock_gcc clk_gcc_blsp1_ahb_clk>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart3_sleep>;
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pinctrl-1 = <&blsp1_uart3_active>;
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qcom,msm-bus,name = "buart3";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<86 512 0 0>,
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<86 512 500 800>;
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status = "disabled";
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};
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blsp1_uart6: uart@7574000 { /* BLSP1 UART6 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x7574000 0x200>,
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<0x7544000 0x2b000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart6>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 112 0
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1 &intc 0 238 0
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2 &tlmm 42 0>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <10>;
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qcom,bam-rx-ep-pipe-index = <11>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&clock_gcc clk_gcc_blsp1_uart6_apps_clk>,
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<&clock_gcc clk_gcc_blsp1_ahb_clk>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart6_sleep>;
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pinctrl-1 = <&blsp1_uart6_active>;
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qcom,msm-bus,name = "buart6";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<86 512 0 0>,
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<86 512 500 800>;
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status = "disabled";
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};
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spi_9: spi@75B7000 { /* BLSP2 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x075B7000 0x600>,
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<0x07584000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 103 0>, <0 239 0>;
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spi-max-frequency = <19200000>;
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qcom,infinite-mode = <0>;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <16>;
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qcom,bam-producer-pipe-index = <17>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_9_active>;
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pinctrl-1 = <&spi_9_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
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<&clock_gcc clk_gcc_blsp2_qup3_spi_apps_clk>;
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status = "disabled";
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};
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spi_10: spi@75B8000 { /* BLSP2 QUP4 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x075B8000 0x600>,
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<0x07584000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 104 0>, <0 239 0>;
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spi-max-frequency = <19200000>;
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qcom,infinite-mode = <0>;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <18>;
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qcom,bam-producer-pipe-index = <19>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_10_active>;
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pinctrl-1 = <&spi_10_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
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<&clock_gcc clk_gcc_blsp2_qup4_spi_apps_clk>;
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status = "disabled";
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};
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spi_12: spi@75BA000 { /* BLSP2 QUP6 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x075BA000 0x600>,
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<0x07584000 0x2b000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 106 0>, <0 239 0>;
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spi-max-frequency = <19200000>;
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qcom,infinite-mode = <0>;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <22>;
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qcom,bam-producer-pipe-index = <23>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_12_active>;
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pinctrl-1 = <&spi_12_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
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<&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>;
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status = "disabled";
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};
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};
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@ -217,6 +217,61 @@
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};
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};
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blsp1_uart3_active: blsp1_uart3_active {
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mux {
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pins = "gpio45", "gpio46", "gpio47", "gpio48";
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function = "blsp_uart3";
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};
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config {
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pins = "gpio45", "gpio46", "gpio47", "gpio48";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart3_sleep: blsp1_uart3_sleep {
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mux {
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pins = "gpio45", "gpio46", "gpio47", "gpio48";
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function = "gpio";
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};
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config {
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pins = "gpio45", "gpio46", "gpio47", "gpio48";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart6_active: blsp1_uart6_active {
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mux {
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pins = "gpio25", "gpio26", "gpio27", "gpio28";
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function = "blsp_uart6";
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};
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config {
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pins = "gpio25", "gpio26", "gpio27", "gpio28";
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drive-strength = <2>;
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bias-disable;
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};
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};
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blsp1_uart6_sleep: blsp1_uart6_sleep {
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mux {
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pins = "gpio25", "gpio26", "gpio27", "gpio28";
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function = "gpio";
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};
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config {
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pins = "gpio25", "gpio26", "gpio27", "gpio28";
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drive-strength = <2>;
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bias-disable;
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};
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};
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pmx_mdss: pmx_mdss {
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mdss_dsi_active: mdss_dsi_active {
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mux {
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@ -931,6 +986,102 @@
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};
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};
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spi_9 {
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spi_9_active: spi_9_active {
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mux {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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function = "blsp_spi9";
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};
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config {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_9_sleep: spi_9_sleep {
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mux {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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function = "blsp_spi9";
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};
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config {
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pins = "gpio49", "gpio50", "gpio51",
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"gpio52";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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spi_10 {
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spi_10_active: spi_10_active {
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mux {
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pins = "gpio8", "gpio9", "gpio10",
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"gpio11";
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function = "blsp_spi10";
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};
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config {
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pins = "gpio8", "gpio9", "gpio10",
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"gpio11";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_10_sleep: spi_10_sleep {
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mux {
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pins = "gpio8", "gpio9", "gpio10",
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"gpio11";
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function = "blsp_spi10";
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};
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config {
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pins = "gpio8", "gpio9", "gpio10",
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"gpio11";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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spi_12 {
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spi_12_active: spi_12_active {
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mux {
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pins = "gpio85", "gpio86", "gpio87",
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"gpio88";
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function = "blsp_spi12";
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};
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config {
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pins = "gpio85", "gpio86", "gpio87",
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"gpio88";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_12_sleep: spi_12_sleep {
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mux {
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pins = "gpio85", "gpio86", "gpio87",
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"gpio88";
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function = "blsp_spi12";
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};
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config {
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pins = "gpio85", "gpio86", "gpio87",
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"gpio88";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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pcie0 {
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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@ -233,6 +233,7 @@
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#include "msm-gdsc-8996.dtsi"
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#include "msm8996-bus.dtsi"
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#include "msm-rdbg.dtsi"
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#include "msm8996-blsp.dtsi"
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&soc {
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#address-cells = <1>;
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