evie/android_kernel_oneplus_msm8998
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clk: qcom: mdss: fix the divider programming for DisplayPort PLL

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Fix the divider programming of DisplayPort PLL with the correct
value. Without this, display doesn't up fine with certain
resolutions on some sinks when link rate is 5.4 GHz.

Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2017-11-15 18:51:05 +05:30
parent b0ba6e4792
commit f96e94247a
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c
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@ -1,4 +1,4 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -128,10 +128,10 @@ int vco_divided_clk_set_div(struct div_clk *clk, int div)
auxclk_div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_VCO_DIV);
auxclk_div &= ~0x03; /* bits 0 to 1 */
auxclk_div |= 1; /* Default divider */
if (div == 4)
auxclk_div |= 2;
else
auxclk_div |= 1; /* Default divider */
MDSS_PLL_REG_W(dp_res->phy_base,
DP_PHY_VCO_DIV, auxclk_div);