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clk: msm: clock-gcc-cobalt: Add clock reset support for additional clocks

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Add the BCR register for the gcc_ufs_axi_clk and
gcc_blsp1/2_ahb_clk clocks.

CRs-Fixed: 1005036
Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2016-04-18 17:22:22 -07:00 • committed by Jeevan Shriram
parent f5a5a7c798
commit ffb7a2d754
2 changed files with 6 additions and 0 deletions
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3
drivers/clk/msm/clock-gcc-cobalt.c
View file

@ -1168,6 +1168,7 @@ static struct branch_clk gcc_bimc_mss_q6_axi_clk = {
static struct local_vote_clk gcc_blsp1_ahb_clk = { static struct local_vote_clk gcc_blsp1_ahb_clk = {
.cbcr_reg = GCC_BLSP1_AHB_CBCR, .cbcr_reg = GCC_BLSP1_AHB_CBCR,
.bcr_reg = GCC_BLSP1_BCR,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(17), .en_mask = BIT(17),
.base = &virt_base, .base = &virt_base,
@ -1360,6 +1361,7 @@ static struct branch_clk gcc_blsp1_uart3_apps_clk = {
static struct local_vote_clk gcc_blsp2_ahb_clk = { static struct local_vote_clk gcc_blsp2_ahb_clk = {
.cbcr_reg = GCC_BLSP2_AHB_CBCR, .cbcr_reg = GCC_BLSP2_AHB_CBCR,
.bcr_reg = GCC_BLSP2_BCR,
.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE, .vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(15), .en_mask = BIT(15),
.base = &virt_base, .base = &virt_base,
@ -1958,6 +1960,7 @@ static struct branch_clk gcc_ufs_ahb_clk = {
static struct branch_clk gcc_ufs_axi_clk = { static struct branch_clk gcc_ufs_axi_clk = {
.cbcr_reg = GCC_UFS_AXI_CBCR, .cbcr_reg = GCC_UFS_AXI_CBCR,
.bcr_reg = GCC_UFS_BCR,
.has_sibling = 0, .has_sibling = 0,
.base = &virt_base, .base = &virt_base,
.c = { .c = {

3
include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
View file

@ -125,6 +125,7 @@
#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 #define GCC_AGGRE1_USB3_AXI_CBCR 0x82024
#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C #define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C
#define GCC_BLSP1_AHB_CBCR 0x17004 #define GCC_BLSP1_AHB_CBCR 0x17004
#define GCC_BLSP1_BCR 0x17000
#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 #define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004
#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 #define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008
#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 #define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004
@ -141,6 +142,7 @@
#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 #define GCC_BLSP1_UART2_APPS_CBCR 0x1C004
#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 #define GCC_BLSP1_UART3_APPS_CBCR 0x1E004
#define GCC_BLSP2_AHB_CBCR 0x25004 #define GCC_BLSP2_AHB_CBCR 0x25004
#define GCC_BLSP2_BCR 0x25000
#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 #define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004
#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 #define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008
#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 #define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008
@ -195,6 +197,7 @@
#define GCC_TSIF_AHB_CBCR 0x36004 #define GCC_TSIF_AHB_CBCR 0x36004
#define GCC_TSIF_REF_CBCR 0x36008 #define GCC_TSIF_REF_CBCR 0x36008
#define GCC_UFS_AXI_CBCR 0x75008 #define GCC_UFS_AXI_CBCR 0x75008
#define GCC_UFS_BCR 0x75000
#define GCC_UFS_AHB_CBCR 0x7500C #define GCC_UFS_AHB_CBCR 0x7500C
#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 #define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010
#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 #define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014