FILLER relock on error recovery may create an alignment that is not
compatible with host controller. When this issue happens, host controller
no longer detects symbols until LINE-RESET is done by host controller as
a recovery sequence. This change disables FILLER symbol relock.
Change-Id: Id7147bfb0de6be45de4936fe3429a9ad76a3868b
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Hibernate entry failures have been observed with some UFS devices.
The UFS PHY Rx termination is not disabled within the specified
RX_Min_STALL_NoConfig_Time_Capability of 15 SI. The UFS device enables
mid-termination after RX_Min_STALL_NoConfig_Time_Capability SI. The
combination of Rx terminated and device Tx mid-termination collapses
the line state to near the differential mid-point. The signal detect
may report the line state incorrectly as DIF-P. The incorrect DIF-P
moves the Rx FSM into the HS-Burst state rather than the intended
Hibern8 state. Fix this issue by setting the UFS PHY's
RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY to 40.
Change-Id: I475e03686831e8131fd7ec1c30e6e8f53a6e188c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
This change adds the UFS PHY initialization table for UFS controller
version 2.2.0.
Change-Id: Ia77dec85433041e2fab3c89df10cc4727e4a47e9
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Hardware programming guide has updated the PHY power up sequence,
this change adds the relevant changes.
Change-Id: I320e38f501cdafc053d47bf2b21ba7f69b1b12a7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
On some UFS PHY HW revisions, UFS PHY power up calibration sequence
requires manual VCO tuning code and its better to rely on the VCO
tuning code programmed by boot loader. This change enables the quirk
to program the manually tuned VCO code.
Change-Id: Id1bb2b28816b8de6df7ca22cda5788288b11328a
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Hardware programming guide recommends one more PHY setting as part
of UFS PHY power up sequence hence this change adds it.
Change-Id: I92f77faa6ca28d6f72d7601344b439ef7596d572
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
UFS PHY auto calibration is not working currently hence add workaround
to have manual calibrated configuration as part of power up sequence
itself. We had another workaround for hibern8 enter/exit to work and it
had required us to save the auto calibrated VCO codes after PHY power up
sequence and then set the PHY PLL in VCO bypass mode. As the auto
calibration is not working and we are already having manually calibrated
VCO codes as part of PHY power up sequence itself, this change removes the
old workaround.
Change-Id: I570ea4f7f8c2f79a06321fb43c8cb01575bf0df0
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up
sequence so make sure that this register gets set to power on reset value
during power up sequence. This is required in case power up sequence is
initiated after this register value got changed to value other than power
on reset value.
Change-Id: Ied8ebf6dc181da9e877427420e1ee4476f1c442f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Due to missing reset in the UFS PHY logic, the pll may not lock following
analog power collapse. As a result the common block of the PHY must be put
into reset during hibernate entry and taken out of reset during hibernate
exit. SW needs to save ave the calibrated VCO codes after the PHY power up
sequence is completed, saving these codes will save substantial time on
hibernate exit (<50us vs. 1.7ms).
Change-Id: Id5f5eab04f1a1f93179cf9e5cdd3c7c8be4b17af
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
UFS PHY power up calibration sequence on UFS controller revision 2.0.0
can't have SVS mode configuration otherwise calibration result cannot
be used in HS-G3. So there are additional register writes must be done
after the PHY is initialized but before the controller requests
hibernate exit. Also as this issue is not present on UFS controller
revision 2.1.0, SVS mode configuration registers are written as part
of the power up calibration sequence itself. This change takes care
of these issues related to SVS mode.
Change-Id: Ib431d98345224db13f1d68197e948bb077c95080
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts,
drop include/linux/phy/phy-qcom-ufs.h]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Some UFS devices send incorrect LineCfg data as part of power mode change
sequence which may cause host PHY to go into bad state. Currently we
workaround this issue by disabling the device's TX LCC but disabling TX
LCC is much more complicated if both host and device supports UniPro 1.6
specification. To simplify the workaround, this change disables the host
PHY's RX LineCfg to skip processing incorrect LineCfg from device.
Change-Id: I1eac56c11dd001eb0c53ba8e16aa512a656ab9ea
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This change adds a support for a 14nm qcom-ufs phy that is
required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: Dov Levenglick <dovl@codeaurora.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
