Add device specific GPU properties for Cobalt.
Add GPU DCVS and bus DCVS plan
CR-fixed: 973565
Change-Id: I6c51be7eeb50c41d4cfa9f9548ebd48888ee1ac5
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: George Shen <sqiao@codeaurora.org>
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
xhci_stop_device() is calling xhci_queue_stop_endpoint() multiple time
and doesn't check return value. xhci_queue_stop_endpoint() can return
error if xhci is already halted or not able to queue command.
xhci_stop_device() waits for stop command completion using
wait_for_completion which wouldn't be interrupted or completed if
queueing of command fails. It results into possible deadlock condition
where usb_disconnect() waits for this udev->lock which is already
acquired by caller of xhci_stop_device() which is set_port_feature().
Fix this issue by handling error condition and making sure that
xhci_stop_device() doesn't wait if queueing of command is failed.
Change-Id: Ica4db17afcd39a7e89fcf985f41760efd2756653
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
As per the hardware documentation, update the voltage regulator
configurations needed for 8996AU CDP. This overrides the settings
done in msm8996-regulator.dtsi.
CRs-Fixed: 978343
Change-Id: I250e5c6e7f6d80ab1415b873c9ed6e405aae0c4c
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Halo HL7509 external buck converter powers VDD_GFX voltage rail
on 8996 automotive CDP. Specify the necessary configuration for
it.
Disable closed-loop CPR operation for graphics CPR controller
until it is verified with this external buck configuration.
CRs-Fixed: 978343
Change-Id: I7d9bdce4c0b381942c6201f80b0970cad8d82ab5
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Halo hl7509 buck converter will be powering the VDD_GFX voltage
rail of 8996 automotive platforms. HL7509 requires an enable gpio
to turn on the external buck. Support it through a fixed
regulator.
Add them to the list of regulators for msm8996. Keep them
disabled by default so that they can be enabled in board specific
files.
CRs-Fixed: 978343
Change-Id: Ib8006e640206a92ac6f227a4a180efbe7d15026f
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Add SET and GET parameter APIs to query speaker
parameters in feedback speaker protection FTM mode.
CRs-Fixed: 974621
Change-Id: I1a51e5033d7836c0c996621593cd2f4dd6982dcd
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
Post processing driver clients can program the dither table in mdp.
If length of the dither table is set to 0, driver will program the
default table. If driver client would like to program the table it needs
to update the length field as per mdp hardware version.
CRs-fixed: 983164
Change-Id: I5e6aaa3d9376884e5ea1fe153cdf2798e3a52d1e
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Add support for CEC commands to suspend and resume the device.
The HDMI core must be kept on when the CEC wakeup feature is
enabled and the device is going into suspend state. Furthermore,
interrupts must be enabled in this state to capture CEC commands.
This allows the device to be resumed later on via CEC wakeup commands.
Change-Id: Ie6fcbc666e4f40335ab8faaa969d4b03aa83e17c
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In the current implementation, the DSI PLL codes are copied from
a CMA memory which has a no-map attribute. Update the logic by
reading the pre-calibrated DSI PLL codes from physical memory
which is re-mapped to virtual memory allocated in kernel using
ioremap_page_range. Once the DSI PLL codes are stored, free the
reserved CMA memory back to kernel.
Change-Id: Iaa0bbd600dd1a18497cd4dfd7830a9bf88ab0ead
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
When DSI panel in unblanked, the driver configures the sources for all
the DSI branch clocks based on the current HW configuration. This
assumes that the clocks would be off when the panel is unblanked. This
may not be true when transitioning to ON state from any of the panel low
power states (LP1 or LP2). This can lead to warnings when trying to set
the clock source while the clock is enabled. Fix this by ensuring that
the clock source is configured only if the panel is not on.
Change-Id: I97f40eaedad203c5aaa0c645105bea2ff962e81d
CRs-Fixed: 975819
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add xlog entry when BTA DONE interrupt is received. And add
proper error messages before panic in few places, to make it
easy to identify the reason and place of the crash.
Change-Id: Ie9e24d2caeff12601058ea3c76af4e3dca0cd09c
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Codec reset gpio configuration needs to be updated
before slimbus master component is initialized otherwise
codec cannot be enumerated on the bus. Add a new platform
device driver to update the codec reset gpio configuration
to valid state (output, drive-strength) before slimbus
is initialized.
CRs-Fixed: 968161
Change-Id: I7227212e6b846d58196718255aa4b0923352d120
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
Update the clock framework to support the setting of post_div for
debug mux so as to divide the clock by post_div.
CRs-Fixed: 977413
Change-Id: I7299bdb0953dcf65fbf2a38b7578e2e54446c0d7
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
There is a line corruption on top of hx8394f panel, which is a
specific issue of hx8394f panel configuration. Update hx8394f
init sequence to fix this issue.
Change-Id: If28cc8dc0c7fa9d979ada92685c1abb6c93ccccb
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Dump the call stack if there is no memory available from the prealloc
pool in order to get the source of the memory allocation.
Change-Id: I0b523e82638410ea679f1d9d3f4bb56703ed9100
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Some platforms support multiple GPU clock plans based on the speed
bin in the efuse. Specify the wake up frequency of each speed bin
individually to wake the gpu at the correct powerlevel.
CRs-Fixed: 967494
Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
While producing snapshot disable all HWCG branches, not only top level.
CRs-Fixed: 978122
Change-Id: I4b01224a0ba46c276115a284a0da6207c7968f72
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
The cluster id flag is passed in from the userspace through ioctl
interface. Ensure correctness of cluster id to avoid out of bounds array
accesses.
CRS-fixed: 977508
Change-Id: I778b962d347b90488b983a15087b13e90ad06688
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Make PM QoS request API generic to pass the type of latency
requirement needed by the client instead of hard coding
latency type. Add latency type as a function parameter.
CRs-Fixed: 972761
Change-Id: Ic912148d2068fe8a758b6a4b3be570ccf870f03a
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
To avoid memory leakage, make change to release ION memory if qseecom
failed to unload TZ app, which is allocated when starting app.
CRs-Fixed: 977073
Change-Id: Ic4c9a7d7a118ff5026ce6ce7769a4c053906ed2d
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Change d743524091501ae60c76b272c45048a17144cc22 ("ARM: dts: msm:
add PM8994 LDO 18 pin control regulator for msm8996") added a new
rpm-smd-regulator device for the pin control version of the
PM8994 LDO 18 regulator. Unfortunately, it specified the same
device node name as used for the original LDO 18 regulator. This
had the effect of removing the original LDO 18 regulator and
switching all of its consumers to the pin control version.
Correct this by changing the name of the LDO 18 pin control
device to regulator-l18-pin-ctrl.
Change-Id: I2311b7c54afa98365e497598f7fb4be787141860
CRs-Fixed: 978138
Signed-off-by: David Collins <collinsd@codeaurora.org>
There is a possible race condition that runtime suspend is being
called after device path bringup. To avoid this race condition,
add a mutex lock during device path bringup to serialize runtime
suspend and resume.
CRs-Fixed: 967442
Change-Id: I268a25b05799c66fc019e19e46939286e54fb514
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
8996 automotive CDP is using different SD card detect GPIO than normal
CDP, update the GPIO number accordingly.
CRs-fixed: 977653
Change-Id: I1b9365e305636f80905604aa9d6cf0a37e815924
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
With USB device mode, USB driver votes for nominal SNOC bus frequency
which prevents system going into SVS. This change reduces SNOC vote
from 120 MHz to 100 MHz to allow SVS.
CRs-Fixed: 975648
Change-Id: I13492cddd8af3f9dea4244e24485556c0efac29e
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
adreno_spin_idle spins for a timeout checking for gpu to idle.
Sometimes due to race conditions the timeout can occur before the
loop is executed. Change the logic to a do-while loop and add an
extra idle check after the timeout before returning failure.
CRs-Fixed: 978122
Change-Id: Idb92a0180dd8cc3e662b1ccf44d69e4bbafb29f1
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
wlan driver transport layer pdev handler needs 128kb pre allocated
memory in a single block memory allocation for transmit/receive
descriptor initialization in wlan startup for the wlan module with
high latency(SDIO) based hardware interface.
CRs-Fixed: 978073
Change-Id: I0dbe047a7b64e96bf32470702d1b3e3088bffcf7
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>
If an ahash request is not final, the result variable of ahash_request
may not exist. In the completion callback function, then, do not
copy the digest result to result variable of ahash_request, if it not
final. Otherwise, crash may happen.
Change-Id: I169218e8658500539b19408eca3afeabcaa4816b
Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Sivanesan Rajapupathi <srajap@codeaurora.org>
cma regions can be allocated for secure use cases where
the virtual mapping is removed. kmemleak scan can try to
scan through this mapping causing mmu faults. Hence free
cma regions from kmemleak scan.
Change-Id: I2cc66423ec9ec539905cc8d07bbc40fa43e695bd
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Add cpu enter and cpu exit log into lpm debug for 32bit.
Change-Id: I88973dbc4f9ffc08f8201059a82a3133fa0db330
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
The worker thread can either be stopped through kthread_stop or could
return from the function on some conditions. Since thread has two exit
points, this is causing a race condition where kthread_stop indefinitely
waits for the thread to exit. Make the thread standalone and always call
do_exit itself to exit instead of stopping it through kthread_stop.
CRs-fixed: 972943
Change-Id: If95cbd6ee895d566887453e98421d1514147441b
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
Add split DSI display support for MSM8996 AU CDP board. It's
using NT25597 dual DSI video panel.
CRs-fixed: 977619
Change-Id: Ibeee5fa903c152c8242a2b27be3d9df9670b762e
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
Set the recommended high bit bank value for all of the various GPUs
that will be programmed into registers by the kernel and/or the
user mode driver.
CRs-Fixed: 970272
Change-Id: Ic0dedbadcd02dd37afce0807ac1118fe7bf10b5d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
On 5XX targets we need to program the bit of the highest DDR bank
into a number of registers, one of which is protected which would
cause problems if the user mode driver tried to write to it.
Specify the high bank bit in the device tree files, set the
problematic register in the kernel and then pass the value up to
the user mode driver as a property and let them program the
other registers. This makes the device tree the authoratative
source of the high bit value which is exactly how it should be.
If the value isn't specified by the device tree for whatever reason
return an error for the property request - that will give the UMD
a clue that the value wasn't specified and they should just set a
default.
CRs-Fixed: 970272
Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For performance improvement avoid multiple writes to channel ring
which is a dma coherent memory. Instead, construct the TRE
(Transfer Ring Element) in local memory and then copy it to the
ring itself.
Change-Id: I36bfae306be2a90c8679d416397a435e638b54eb
CRs-Fixed: 977590
Acked-by: Ady Abraham <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Enable CSID IRQ dynamically and add sof recover logic,
in case kernel get sof freeze hints from userspace,will
enable IRQs to monitor the status of moduels,if sof recovers
after 2.5 secs then kernel get MSM_SD_UNNOTIFY_FREEZE to disable
all the IRQs.
CRs-Fixed: 973732
Change-Id: I7aa6dcd60e0858258c40c3d6517e2974e6e2b722
Signed-off-by: Ramesh V <ramev@codeaurora.org>
The pm_qos framework passes down a mask of cpus for which the qos has
changed. cpuidle driver uses this info to wakeup only those cpus for the
new qos to take effect. This would prevent waking up cpus for which the qos
values remains unchanged.
Change-Id: Ibb79937674a8f16920c6b8f224a21d2f72a0f9ce
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Add a devicetree property disable-busy-time-burst to
disable ceiling threshold in the governor. The ceiling threshold
cause busy time burst that switch power level for
large frames based on busy time.
Change-Id: I44f8a51e0aa49bb0b2210703f57874fd5f219c18
Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
There is a race condition when a read is queued and a
subsystem restart occurs before the read can finish. The
read will call read_done on a freed handle. This fix
changes the ss_reset lock to a rwlock and extends the
critical sections in the read and write data functions.
CRs-Fixed: 969026
Change-Id: I7726e4bbea7447ad96df725b50e4eff1ec67607f
Signed-off-by: Chris Lew <clew@codeaurora.org>
Add sharp 4k dsc cmd mode panel configs and enable it for
msm8996 mtp, cdp and fluid. Add partial update for support
with roi alignment width as 1080 and y-slice as 8,
as per the spec. The panel is also capable of supporting
y-slices 8/16/24/32/48/3840, but width/x-slice cannot be
modified.
CRs-fixed: 974677
Change-Id: I6e7e96178db604f71a16f1f656e38d66d37eca66
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Fix the panel on command for sharp 4k dsc video model panel
according to panel spec. And remove few parameters from the config
file, which are unnecessary for video mode panels.
CRs-fixed: 974677
Change-Id: I92cb0c5a30206b6b788cdfe2b0316e4bf77d1828
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
The GPU GDSCs need to be turned prior to enabling the graphics
clock and programming the CRC registers. Add that support.
CRs-Fixed: 974342
Change-Id: I4f97c10c383f79490c8dc428ef5ffb1040adc18d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
When configure the scratch buffer, wrong pingpong bit location is
programmed. So the VFE hardware can still write to the same buffer
which has been diverted to other camera compoment. This cause the image
corruption.
Change-Id: I6d5cfe0c00a237efb3ab3dff87459341736d45a7
Signed-off-by: Jing Zhou <jzhou70@codeaurora.org>
Allocated memory is not getting freed in remove request.
This change is to free the memory allocated to avoid memory
leaks.
Change-Id: I1225d492b7f58f8bda2621ec0bb2bd201d8dee6c
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
The camera drivers for msmcobalt are not ready yet for
presilicon verification, Hence disable them from
the dtsi.
CRs-Fixed: 974351
Change-Id: Icdf65d0aabbac5661a803d2a3d6d04f78071d963
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
