This enables the WA for vph_pwr_2p5_ok signal remaining invalid.
CRs-Fixed: 1053543
Change-Id: I58c23adace7c4c29f352edb706666effe69dc8ad
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
The LCDB module does not sample the vph_pwr_2p5_ok signal if it drops
low when the module is off. It will continue with the last known
state of vph_pwr_2p5_ok which could cause a problem if vph_pwr_2p5_ok
is indeed low. Fix this by re-enabling of the module to activate
the vph_pwr_2p5_ok signal sampling.
CRs-Fixed: 1053543
Change-Id: If0950140cae12c92bb6be428b22400b492f823e4
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Provide means to set ship mode on smb138x charger. While in parallel
charger mode make the main charger set ship mode on smb138x before
calling ship mode on itself.
Change-Id: I9b96b425829520d95632aa32d2297940cca5e254
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
When HDMI controller is configured as non-DVI with CEA mode, SDE
driver needs to program AVI, VSIF and SPD information into HW to
generate correct info frame.
CRs-Fixed: 2010135
Change-Id: Ib218761c63b13aa229fc24519ceb9ccd0bd34ce2
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add a private HDMI bridge implementation for SDE. This is
intended to support new HDMI features specific to SDE driver.
CRs-Fixed: 2010135
Change-Id: I0269b1ff79d8be4f48643a9e4e904427791ac1ac
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
This reverts commit <c3e05abca5fabd7580be1378c5165a8b8f523f98>
(<drm/msm/sde: fix color component order>).
Color component order is specific to the rendering framework as well.
This change reverts the commit mentioned above to take other
frameworks into account which have different endianness.
Change-Id: Ic3135d5742dd4cf999f2d7271fc56ee46c74a353
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
For modem SSR, APPS needs to halt modem consumer channels after
shutdown to make sure GSI FW does not access any modem's memory.
Change-Id: I6889a2ad509e0b1104ef8c3f65f24fe39b10745d
CRs-Fixed: 2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
Expose a new API from GSI driver to allow client driver to
disable channel for other Execution Environment.
This API will be used as part of SSR cleanup.
Change-Id: I3b9400643aff76ca2195a597aba9ea18aab3085e
CRs-Fixed: 2008582
Acked-by: Ady Abrahan <adya@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
When the PD voltage changes AICL needs to be rerun to increase the input
current. Do it.
Change-Id: Ifa49547037d17c3ec2f01b6ac70faa310585825a
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Enable watchdog node for sdm630 which is used to detect system hang.
Change-Id: Idfb307dd991e17e0030921e03c6f8a04afb9bc1d
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Added CONFIG_CORESIGHT_CTI and CONFIG_CORESIGHT_CTI_SAVE_DISABLE
in perf_defconfig of SDM660 to enable cti without save-restore
functionality for CPU cores.
Change-Id: I19a2fb8a3097bac910bb5e50c9a80d84f03098d3
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
Added CONFIG_CORESIGHT_CTI_SAVE_DISABLE in kconfig of
coresight to choose CTI without save-restore functionality
for CPU cores.
Change-Id: I48128fbeda293a73d78946b8c222b5d0393c7595
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
To avoid running into issues with the MMNOC RCG being enabled due
to an enable request from a secure world entity whilst the HLOS code
has disabled its parents, park the RCG at CXO when its disabled.
Change-Id: I98e2efaed01ee4e92a457c56f2e276985882dbbb
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If the RCG frequency table does not have CXO as one of its supported
frequencies, and if a client calls clk_enable on it prior to setting
its rate, the current RCG code would configure it to the lowest
supported frequency instead which would then lead the subsequent
call to update the configuration to fail because the parent PLLs are
not active. Correct this behavior. Also update the index in case cxo_f
frequency table is used for rcg configure.
Change-Id: Ib2c09f9f503724bafd32b963b5b0ea84da7c4b7b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Not all MHI hardware channels support burst mode, add
support to enable burst mode per channel basis.
CRs-Fixed: 1027069
Change-Id: Icd3061f1a1a4b4b3dab8f9fe3b989a8afefd18b2
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add support for new MHI hardware channel 102 to be
use by MHI clients as ADPL channel.
CRs-Fixed: 1027069
Change-Id: Ib3c2019fc269064d097bb7f40f01d4580e63a603
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
MHI transaction status stores the OVERFLOW status
received from device. MHI clients uses this
status to determine overflow buffers, do
not clear the status.
CRs-Fixed: 1042516
Change-Id: Iaaff06c1c39775d6a33ca17851f1e1579b2a2ecb
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
SDE rotator uses V4L2 target. Currently mdss_smmu_request_mappings
is defined only within the FB driver. For targets not using FB
this shall cause compilation issue.
Add definition of mdss_smmu_request_mappings for DRM based devices.
Change-Id: I26ef267802845236193b4c2688712e37a178e6cb
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
If the set_cs() call is made when the device has suspended then don't
try to make the register writes to force cs and return back to the
framework. Also remove the runtime PM calls from set_cs, these should be
done in the prepare/unprepare_transfer_hardware calls from the framework.
Modify the prepare_transfer_hardware_call() to fail if the runtime
framework is not enabled and in addition don't try to call the runtime
suspend callbacks from the system suspend callback as this could race with
an on-going SPI transfer.
Change-Id: Idc714b1024c1f181a4db59d5552d7ab9100c511f
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Currently the notifier does not respond to main psy changed events, so
changes in ICL will not schedule the status change work. Furthermore,
the status change work does not re-run the FCC splitting which is
dependent on the settled ICL.
First, add the main psy as one of the triggers for the status changed
work. Second, re-run the FCC and FV voteable elections to re-split the
FCC based on the new ICL.
Change-Id: I1f5f2e176ec470c9c71ff4a0787ffa0cc5828ebc
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Initialize remote_host value for smem corner case where
variable can be used without being set.
CRs-Fixed: 2004073
Change-Id: Iec3b0d66e7f557efa7167bdc2c1be9b02dcd4e96
Signed-off-by: Chris Lew <clew@codeaurora.org>
The maximum PM8998 S13 voltage is 1.136 V. Update the
regulator-max-microvolt property for the PM8998 S13
device to reflect this.
CRs-Fixed: 2010419
Change-Id: Ic9cbd802fed8b0b48c872341efb429f0616b423a
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Initialize values for variables that may be used with out
the value being set in glink corner cases.
CRs-Fixed: 2004073
Change-Id: If0e813bf1601dd6c1288bc22864ddd2fb3dbf90f
Signed-off-by: Chris Lew <clew@codeaurora.org>
When checking for available spaces, check available spaces on
both bounce buffer ring and transfer ring and return min.
Change-Id: I9208b46c32821de3f5d9e3d828087d7bc29b9546
CRs-Fixed: 1055681
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add missing state MHI_STATE_RESERVE to MHI states
look up table.
CRs-Fixed: 1049595
Change-Id: I9a6bd2750f81f6cabc1e7b5aff488b4a01f7897d
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
APR client waits in a waitqueue for glink to queue intents.
On receiving notification about availability of intent, wake_up
should be called on the waitqueue to wake up any waiting APR
client.
CRs-Fixed: 1096481
Change-Id: I5a2b902fa831709092be1a9a3073b8d784adba81
Signed-off-by: Vikram Panduranga <vpandura@codeaurora.org>
If two ioctls are triggered with different commands,
there is a possibility to access freed confidence level
memory. To resolve this acquire lock in ioctl.
Also release mutex lock properly in error cases.
CRs-Fixed: 1103085
Change-Id: I7d6b2eff21c8297e5f0755a0c141254be32f777d
Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
Currently, return value for SMCINVOKE_IOCTL_INVOKE_REQ IOCLT is mixed
with error generated by client. This does not seem right because client
does not understand kernel error code and vice versa.
Change-Id: I77278700c4927facf7aba92a11bfde29b1e8eb38
Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org>
Get the iova for a buffer object from the context
specific address space instead of always defaulting
to the global address space.
Change-Id: Id38c2ca2d6bad334beab53d8bcf8eb5cf5b1bb99
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
Return the current status of the fence (0 for retired, -EBUSY for
active) if an absolute timeout of 0 is passed to MSM_IOCTL_WAIT_FENCE.
This allows the user space to check the status of the fence without
an awkward timeout or an inadvertent kernel message.
Change-Id: Ic0dedbad66adfabed24aeb6692abb2765ee37f24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The PFP/ME and GPMU memory needs to be GPU accessible but it
does not need to be written by the GPU. Mark them as read-only
to avoid corruption.
Change-Id: Ic0dedbadc848f0a6693a4e57567077bbab38e9a5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There isn't any need to be in secure mode when executing the GPMU
initalization so swap out to eliminate it as a variable when
GPMU init goes broken.
Change-Id: Ic0dedbad07b8cde80e257f71999002e9cbc47c24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enable pm_runtime for the GPU to keep power collapse from hitting
us while we expect the GPU to be powered.
Change-Id: Ic0dedbad693f1d01776a87bc7a145a65510ac3fb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
If we do not enable the iommu clocks at attach time they might
be shut off automatically by other devices power collapsing which
would affect our ability to switch the pagetable dynamically.
There is little power downside to just leaving them on all the time,
or at least as long as the main device is attached (in other words,
all the time).
Change-Id: Ic0dedbad8f6d2ee2a2cb9516e062af2421d91052
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The overrun check for the size of submitted commands is off by one.
It should allow the offset plus the size to be equal to the
size of the memory object when the command stream is very tightly
constructed.
Change-Id: Ic0dedbadec41fb8be84d7522b4dc923dbd537ce5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
When a fault happens on the Adreno GPU we want to collect
a considerable amount of information to diagnose the problem
including registers, caches, and GPU memory structures (ringbuffers,
etc).
The snapshot collects all of this information following a GPU fault
and encodes it into a binary file format that can be pulled from
debugfs or extracted from a memory dump.
This may seem a duplication of other debug methods (the ->show
functions for example) and while that is true for small numbers
of registers the snapshot goes much further - it collects hundreds
(thousands) of registers in addition to memory and other structures
that would be impractical to dump as ascii. The binary format allows
for the snapshot to be easily shared and post-processed in different
ways to extract patterns.
Add the basic snapshot infrastructure and enable ringbuffer, register
and shader bank collection for A5XX targets.
Change-Id: Ic0dedbadcf0513096d05870f522ac73da74ceb31
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Change-Id: Ic0dedbade1264785b3436099e638a5678a62818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Update the list of the A5XX register ranges that can be read on a
hang. The new list adds some registers that were previously missed,
and omits registers that are write only.
Change-Id: Ic0dedbadaf6969892c0563d9cfd8fa2869008417
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Instead of using a fixed list of clock names, use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Change-Id: Ic0dedbad629743ff078177c301ffda3dbce88d3c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses.
Change-Id: Ic0dedbad3769801b62152d81b37f2f43f962d308
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more reliably mapped into the
instance's GPU VM space without conflict.
To support this create a new dynamic domain (pagetable) for each open
DRM file and map buffer objects for each instance into that pagetable.
Use the GPU to switch to the pagetable for the instance while doing a
submit.
Change-Id: Ic0dedbad22d157d514ed1628b83e8cded5490dec
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighborhood IOMMU driver.
Change-Id: Ic0dedbaded3a9e57a7fbb8e745c44c183f6b4655
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Change-Id: Ic0dedbad3761b0f72ad6b1789f69458896214239
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Allow a domain to opt into allocating and maintaining a TTBR1
pagetable. The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region.
By example, given a TTBR0/TTBR1 virtual address range of 36
bits the memory map will look like this:
TTBR0 [0x000000000:0x7FFFFFFFF]
TTBR1 [0x800000000:0xFFFFFFFFF]
The map/unmap operations will automatically use the appropriate
pagetable for the given iova.
Change-Id: Ic0dedbad2b2c58cd9c47ce31356472e0463d4228
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing by default but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
possibly using addresses above 4G for those targets that support them.
Change-Id: Ic0dedbad7e527c4b1fe87878e943619c5e0ad869
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Change-Id: Ic0dedbad6c62d6859c90764245437c222d61f00d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Change-Id: Ic0dedbad428360d23768d52b585021237c6bc3d3
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Remove the IOMMU_WRITE bit from buffer objects that are
marked MSM_BO_GPU_READONLY. Add a new flag (MSM_BO_PRIVILEGED)
to pass through IOMMU_PRIV for those IOMMU targets that support
it.
Change-Id: Ic0dedbad8d9d3f461a47ea093fad3fdd90f46535
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Change-Id: Ic0dedbadca31e835f014037ea3f9741048df3b98
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
