Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while it is being written. This isn't a huge deal
with a single ring (though technically the hangcheck could assume
the system is prematurely busy when it isn't) but it will be rather
important for preemption where the decision to preempt is based
on a non-empty ringbuffer. Without a shadow an aggressive preemption
scheme could assume that the ringbuffer is non empty and switch to it
before the CPU is done writing the command and boom.
Even though preemption won't be supported for all targets because of
the way the code is organized it is simpler to make this generic for
all targets. The extra load for non-preemption targets should be
minimal.
Change-Id: Ic0dedbad83247c3e77de6f4f24bbb97db10e5edd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add the infrastructure for supporting multiple ringbuffers.
Change-Id: Ic0dedbada90ec5c4c8074ffce33c3fe275b0cda1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Return the base address of GMEM in virtual address space as
a parameter.
Change-Id: Ic0dedbad3b849052313e4673efcf6c22bc81f21f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Change-Id: Ic0dedbadacef5e866bd37a332019f1133f1def49
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Change-Id: Ic0dedbad543df80fdc4b74cd1cd924e9b8534b44
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add support for the A540 GPU which is a revision of the A530 target
with somewhat more complicated power management support.
Change-Id: Ic0dedbadeca628809b6de7c1843f665ecdc427fe
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Bring in a new revision of the rnndb register to fill out some A540
registers.
Change-Id: Ic0dedbad0daf9ad2301479354a83c05bdc301163
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
In the current code the probed configuration is pretty light and it
can be easily probed at boot time and stored in a config struct.
As more features come online the configuration becomes tougher and
more platform specific. It makes sense to do the configuration in
real time so move the majority of the config over to adreno_gpu and
probe at load.
Change-Id: Ic0dedbade871aae2d39e6b036a5e73e4347fc7ca
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
trustzone using the PIL loader to upload the binary and access
to the special register is blocked with hardware protection.
So in summary, to do secure mode correctly you need 1) a friendly
trustzone, 2) PIL loader support and 3) a verified zap shader.
For targets without secure support there is an out: if the
trustzone doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. Unfortunately we don't have any good way to figure out
at runtime if the trustzone is secure or not so we use a cheat.
If there is a zap shader specified in the device tree for the
target, we assume that the trustzone is secure. No zap shader
definition means that the target is not secure. The downside
of course is that if you guess wrong you trigger a XPU violation
which usually ends up in a system crash but thats a problem
that shows up immediately.
Change-Id: Ic0dedbad8738ad1fac8a7bb8d76e1988aa49f2c8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Most 5XX targets have GPMU (Graphics Power Management Unit) that
handles a lot of the heavy lifting for power management including
thermal and limits management and dynamic power collapse. While
the GPMU itself is optional, it is usually nessesary to hit
aggressive power targets.
If the GPMU is to be used a filename and minimum version are
defined in the device tree. The GPMU firmware needs to be loaded
into the GPMU at init time via a shared hardware block of registers.
Using the GPU to write the microcode is more efficient than using the
CPU so at first load create an indirect buffer that can be executed
during subsequent initalization sequences.
After loading the GPMU gets initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.
Change-Id: Ic0dedbad8d899177919b71500f2e944b187e87c0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add support for the A5XX family of Adreno GPUs.
Change-Id: Ic0dedbad665ef9d0f2cdb32a33eef9fe3fd7aa5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Verify that the GPU is valid before calling any ioctl functions
that might need the priv->gpu member. Standardize the return
code (-ENXIO).
Change-Id: Ic0dedbad015a531b792e0b94cb61e0570b691de8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in messing with things.
Change-Id: Ic0dedbade543a2253b88acf46a8f8e062ae7faf9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Change-Id: Ic0dedbad8a4543428372fe3fef9503cedd1eef6e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
The upstream DT model presumes that the iommu phandle is in the main
GPU device node. The downstream model defines sub-nodes for the
IOMMU devices. In order to get the right device to attach the IOMMU
domain to we need to do a bit of searching.
First, check in the top level node. If that fails, then start walking
the port list passed in the attached function - hopefully one of those
will have the right device - if found, use that to attach the domain
and breathe normally.
Change-Id: Ic0dedbad4a1852d2ff204031bd360e0b7960805a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Newer Adreno GPUs are able to support 64 bit virtual addressing. To
prepare for this brave new world switch all IOVA related variables
and members to a uint64_t container. This is harmless for the
display and older targets that do not have 64 bit addressing because
a 32 bit address is just a 64 bit address with lots of zeros. To
avoid ambiguity and compiler oddness make sure to use
lower_32_bits() and upper_32_bits() everywhere the IOVA is used to
ensure that you get what you expect.
Change-Id: Ic0dedbad23322fae32509c1f4d75d9b4e2863081
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Change-Id: Ic0dedbad4495f02a21135217f3605b93f8b8dfea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
PM_QOS will put the interrupt where it wants to and we're okay
with that.
Change-Id: Ic0dedbad5294d51a55125a0021f7dcc3b185de02
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Add LMH DCVSh mitigation support for kernel thermal driver for sdm630.
It enables KTM to request frequency mitigation to LMH DCVSh hardware
block.
Change-Id: Ia546f004416dff2da7c6560b8e582eac563d3f8e
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Enable LMH DCVSh driver for sdm630. It adds information about
the interrupt generated by the LMH DCVSh block for sdm630.
Change-Id: I16a5f9f0737e64b4ed0e39e0624afb64fbf623e7
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Update LPM parameters latency, ss power, time overhead and
energy-overhead with the values measured at minimum frequency.
Change-Id: Id5fc176a02978c54e4cb4faec4dffca83a7cbea5
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Some drivers (e.g. OLEDB) would need to know about LAB_VREG_OK
status from the LABIBB module. Hence, add support for the
notifier callback so that required drivers can be notified about
LAB_VREG_OK status.
Change-Id: Ib60c94c7557ee6ffb7595dee5bd268bb76faaf6e
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
msm8998 needs an additional 5V pin to be
enabled to power the HPD circuit. This change
enables the support for this pin.
Change-Id: I42f91265ce56ff5505e3d9c2382858fe6c1be52b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
When HPD is enabled in DTSI for HDMI display, driver needs to poll
the HPD status change and report event back to user space.
Change-Id: I6dd2f3078875698ff8cfd7bdb7cfd662e85eec9b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Sde io util provides apis for clock management,
regulator management, gpio, register read/write,
etc. This enables the APIs callers to manage
the hardware resources. This patch adds the
io util API support to msm drm driver.
Change-Id: I3b61d42d15659eccde4303e0f68615620b344075
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Sometimes the HDMI is treated as non-pluggable display in auto
use cases. Add support to configure it through dtsi file, and
also provide timing parameters for the customized modes through
dtsi.
Change-Id: I2326b6c43cb7e6361be1f14d25f0e2e493c94177
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Include SDE DTSI for MSM8998 chipset. This
ensures that boards and targets using SDE driver
will use the new DTSI.
Change-Id: I9dfe8c48efbee5cb4f85fe684a06a2023abfda53
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
APQ8098 mediabox shall use the new SDE driver.
Disable the mdss_mdp device node on APQ8098 mediabox to avoid
duplicate probes.
Also make HDMI as the primary display for APQ8098 mediabox.
Change-Id: I9bea09473fccf2bf3048f0e0428b94bb16be3eda
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Rename mdss_mdp to sde_kms in the device tree to reflect the
new display DRM driver terminology and add support for HDMI TX
device node
Change-Id: Ide5dc6a5939945a3e993eca650c66a56f3955140
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Updating min frequency for memlat voting from 633MHz to
902MHz to avoid intermediate DDR frequency switching on
SDM660 target.
Change-Id: Ic68cbd15757bdc5ee1dbaef1d850a699c614837c
Signed-off-by: Nikhil Kumar Kansal <nkansal@codeaurora.org>
Add MDSS reg bus scale properties for sdm660 and sdm630.
These votes are required for faster reg access especially
in cases like histogram/gamut where we read large number of
registers.
Change-Id: Ia7aac81216b4138b583b37a938643eb950b5dcfc
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
In existing implementation elf region was being clearead before memory
access to firmware region assigned to HLOS. So to avoid it using
separate function which will be called only when HLOS is the owner.
Change-Id: I8bb22e4dbe3e1f898678d0c0f6e60268b88fc150
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Update the fuse corners supported for APC0/1 CPR instances of sdm630
as per the new fusing scheme.
Update speed-bin 2 frequency for TURBO_L1 to match the clock node
mapping.
Update the ceiling voltage limits for interpolated voltage corners
to that of their next fused voltage corner.
CRs-Fixed: 2008764
Change-Id: Iff104afa9750ba4be131cf142fc9eec01910678c
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add INT3_MI2S interface support for source tracking as INT3_MI2S_TX
is used for capture in the internal codec for SDM660.
CRs-fixed: 2007623
Change-Id: If0c72ad0942fc56b2778b831de019052c8fe31c0
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
Timeout errors can occur because of execution error in device during
execution of last command. For errors encountered while executing
commands in card, like cmd46 or 47, the card will stop execution and
wait for the next command from controller to return error information.
If controller sends no command, then a timeout error will occur. To
retrieve the error information in card, send status command must be
sent. In case a non-timeout error like RED error is detected, there
is no need to send CMD13 to card as the error information is already
present in the Resp Arg register.
Change-Id: I6ac0d3db834a3d5a6c67ee08d6232240c35714ff
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
Update the number of fuse corners used for APC0 and APC1 CPR
instances of sdm630 as per the new fusing scheme.
CRs-Fixed: 2008764
Change-Id: Icee251c350c102c698c2f60f3189e5aecf2dc7b1
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
When exiting low power modes (M3) do not reset
the DB Mode state if DB mode preserve flag is
set for channel.
CRs-Fixed: 1022868
Change-Id: I6557d28afe9d0ac11b76c683ffba76d7d6ffd377
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
In order to avoid being out of sync between MHI client
and MHI host, host shall not reset the doorbell modes for
hardware channels during MHI_M3 state transition abort.
CRs-Fixed: 1023725
Change-Id: I6c742fc968fd57d71a86039bf1f3f65b1362bc90
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Add camera node include rear,aux and front camera to
support the msm8998 QRD HDK device.
Increased the drive strength of mclk clock.
Change-Id: I6c8a3f3c69ca2bc2e3b54b46324525c67d0a2fd3
Signed-off-by: Wei Ding <weiding@codeaurora.org>
To avoid any race conditions between MHI_M2 state
transition and MHI_M3 state transition lock the
entire MHI_M3 transition using xfer_lock.
CRs-Fixed: 972390
Change-Id: I7c2e1b7b3966dc5fb8bf2f91bce734bbc58c6fd7
Signed-off-by: Tony Truong <truong@codeaurora.org>
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
There are instances when MHI channel context read
pointer can be accessed simultaneously by different
CPU cores. To make sure read pointer updates visible
to all cores, add a memory barrier after completion
of MHI ring operation.
CRs-Fixed: 966338
Change-Id: Ifc8c4cd7595fed9049009c42420a665fb170079f
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Validate the channel prior to proceeding further.
Unlock spin lock before jumping to error handler.
CRs-Fixed: 1016969
Change-Id: Ie3328f878b582a333ae15f3b950c258ec42fd768
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Instead of printing enum index convert MHI_STATE
enum to text representation for easier interpretation
of debug logs.
CRs-Fixed: 1012249
Change-Id: I97a9a7ff293c739531d8197334a0f0a35bf20419
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
Possibility exist when handling a DB MODE event another
core to queue a TRE to same channel. During that time
CC ctxt WP may get updated, however DB MODE event thread
still be using a stale WP. Add a lock to synchronize
DB MODE event thread and queue TRE thread.
CRs-Fixed: 1005752
Change-Id: I7f285da8751a867a1c3d651466537368799eb657
Signed-off-by: Sujeev Dias <sdias@codeaurora.org>
