Some regulators support get_voltage and some support get_voltage_sel
operations. Do voltage change propagation only when the current
regulator has a minimum dropout voltage specified or if the current
regulator lacks both get_voltage and get_voltage_sel operations.
CRs-Fixed: 2018399
Change-Id: I24cc880d6a61c2cb489897d39a1b63199749c98d
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Add a VDD_APCC CPR boost corner of 1996.8 MHz for the power
cluster on MSM8996-Pro speed bin 1 parts.
Change-Id: I9bf29cdba47918770dbef5cd1f2631afccf26221
CRs-Fixed: 1010722
Signed-off-by: David Collins <collinsd@codeaurora.org>
Change the MinSVS fuse corner to virtual corner mapping for the
power cluster and performance cluster on MSM8996-Pro chips with
CPR fuse revision 2 or greater.
Change the mapping according to the following:
Power cluster: 1 (307.2 MHz) --> 3 (460.8 MHz)
Perf cluster: 1 (307.2 MHz) --> 4 (537.6 MHz)
Change-Id: I6b6ee6225d43605ad0f5ae1e16061acf12b49927
CRs-Fixed: 1004373
Signed-off-by: David Collins <collinsd@codeaurora.org>
Update the VDD_GFX CPR open-loop and closed-loop voltage
adjustments for MSM8996-Pro chips based upon characterization
results. This ensures stability and minimum power consumption.
Change-Id: I89b79f92bcb4cc54a050f8b0ba17f76ff471838f
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
Update the VDD_APCC CPR open-loop and closed-loop voltage
adjustments for MSM8996-Pro based upon characterization results.
This ensures stability and minimum power consumption. Reuse the
CPR revision 1 adjustment values for future CPR revisions (2 - 7)
for forward compatibility.
Change-Id: I42f7b696987102a38db324a1c515f1c6f01e6d45
CRs-Fixed: 989555
Signed-off-by: David Collins <collinsd@codeaurora.org>
As per msm8953 design, APM state machine could take more
than 200us for mode switching. Increase SW timeout constraint
value to 500us.
Also, update the mask used to check APM switch status.
CRs-Fixed: 992695
Change-Id: Ie0f8733fb5b39172fb14547292cbd05689a50230
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
To accommodate speed bin 2 and fuse revisions associated with it
increase the fuse combo count from 16 to 24. At present, this is
needed for msm8996proAU SOC.
Change-Id: Ie781ffda433d491a38695caa5e55ec1ec7ff9b4a
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
To accommodate speed bin 2 and fuse revisions associated with it
increase the fuse combo count from 16 to 24. At present, this is
needed for msm8996proAU SOC.
Change-Id: I8555162eab2c6bfead2e0762f28525e0aa56cf10
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Temp_adj_en instantaneously reduces the voltage and quotient
when temperature enters into corresponding band which may cause
an aggressive reduction in voltage. Avoid this by not configuring
temp_adj_en bit, this only reduces the quotient and allows CPR to
react to the reduced quotient. Use temp_adj_en bit only when both
temperature based and core count based adjustments are desired.
CRs-Fixed: 1051076
Change-Id: Ia42dbdd095e51bf9b9b7e865c104dcbe8f4219da
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Update Multimedia1 FE to support up to 8 channel audio capture.
CRs-fixed: 2028896
Change-Id: I838ecd690fcdeef411d35a5facbe9c40a76b68c3
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
The commit 639277b6c73c ("regulator: spm-regulator: Add additional
settling delay for FTS2.5 SMPS") incorrectly changed the usage
of 'uV' variable. The local 'uV' variable holds the correct voltage
level to be scaled up/down. Use it instead of vreg->uV.
CRs-Fixed: 1036738
Change-Id: I52540237a4db79c149409c6017ffc750b5abddd2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Based on characterization add 70us settling delay on the voltage UP
to account for warm-up time and ramp-up delays for 0-10% and 90-100%
of the voltage value.
On the voltage ramp-down side add the stepper slew-rate delay and
and an additional 70us margin to avoid voltage updates while the
stepper is in progress. This could lead to voltage over/undershoot
due to buck-internal synchronization failure.
CRs-Fixed: 1036738
Change-Id: Id4230be9c4c981758bbf6860bab1f487a3b57f85
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
Use scaled gate count (GCNT) for aging measurements to reduce
the noise effect on aging data. The amount of scaling depends
on the noise effect observed in characterization results. Use
a selected scaling factor value to derive the gate count (GCNT)
used for aging measurements.
CRs-Fixed: 1025832
Change-Id: I0eb3fb08d51ddca5cd4c08e26bc83eb9f66fd3ed
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
* changes:
clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate
clk: msm: clock-alpha-pll: Allow interrupts to be enabled during set_rate
1.can: Don't sent fw_br command
Older versions of rh850 get stuck when
fw_br command received.
2.can: Fix buffer calculation
3.can: rh850 support for CAN FD
This change enables dual mode for CAN raw frames and also CAN FD for property transfer with up to
64 bytes payload for both transmit and receive.
4.can: rh850 CAN FD backward compatibility
This change enables backward compatibility for previous versions of VNW framework to use legacy raw frame mode.
5.can: rh850 support for AMB mode
This enables the AMB driver mode to support
CAN FD frames sent while driver mode is AMB
Change-Id: I0b6939f29ebabeebe2fd32a26fcc67c4386a6cb4
Signed-off-by: Bruce Wu <brucewu@codeaurora.org>
Add speed-bin 2 to support the fmax of 1.9GHz and 1.59GHz
for perf and power clusters respectively.
Also add speed-bin 2 to support the fmax of 510MHz for GPU clock.
Change-Id: I085d816474fff3a6d76db1fdb969b6a762867df7
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Add the CPU and GPU clock frequency tables in device tree
to support MSM8996 auto. These overrides apply for both
v3 and pro based msm8996AU.
CRs-Fixed: 1039602
Change-Id: I092c0767570cf500886b75823f24346097676473
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add TERT_TDM_RX_4 BE DAI link into automotive sound card
DAI link array. Add kcontrols for channel and bit format
configuration for TERT_TDM_RX_4 BE.
CRs-fixed: 2018097
Change-Id: I1fef2f6a799aeeee0752f3ae2462dcd26a1d66c9
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add TERT_TDM_RX_4 DAI in the TDM TERT RX entry and automotive
sound card entry for msm8996 automotive ADP/CDP platforms.
CRs-fixed: 2018097
Change-Id: Icbb2e9622fb58995fd063965a108d3e5fbaf42ea
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add support for additional frequencies for the qspi_ser_clk_src
on msm8996.
Change-Id: I4efa0ad4dc3f68a0c54bd4cf7ee77b4c78be4be1
CRs-Fixed: 994014
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Add support for 5 and 7 channel for TDM hw param configuration.
CRs-fixed: 2021342
Change-Id: I933d5aa29c5c5578c884a3533772747db721fc0f
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add support for customized sound card that uses customized
TDM slot mapping and DAI links for automotive platform.
CRs-fixed: 2020063
Change-Id: I887b33d23d2af8af61cf15b499d14afbc9544e37
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add route from Multimedia FE to TERT_TDM_RX_4 BE.
CRs-fixed: 2018097
Change-Id: I22de6c7059ae40956d82176edc130047bd2921f4
Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
Add the pinctrl clock for ln_bb_clk to the GCC driver
for MSM8996.
CRs-Fixed: 1063062
Change-Id: If85a0dbb26e350588cbd6614c032bf208a205be2
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
The CPU that is disabling the alternate PLL may also need to
handle CPR interrupts. Allow the CPU to handle interrupts
during the set_rate operation.
CRs-Fixed: 960701
Change-Id: I63d7ce3e3dd2b559c4db383b64faa9335c404576
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Some PLL implementations depend on the CPU being able to handle
certain interrupts in order for the set_rate operation to
complete. Allow interrupts to be handled in the set_rate op.
CRs-Fixed: 960701
Change-Id: I6fda5ed9eb7d6f2e2cd91c58ebabfd7bc1c8a2fc
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Add speed-bin 2 to support the fmax of 1.9GHz and 1.5GHz
for perf and power clusters respectively.
Also add speed-bin 2 to support the fmax of 560MHz for GPU clock.
Change-Id: I9bc547b0f8a2f2c7cad04ec8c967ed580755ae75
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
